JPS6419580A - Dual port memory circuit - Google Patents

Abstract

PURPOSE:To accelerate a serial clock period faster than ever, by setting an internal serial address generated from a counter circuit at an address larger by one address than an external serial address. CONSTITUTION:Data on a bit line BL is transferred to and held by a serial data register 3 at the time of transferring the data, and the data read out by a first serial clock phi is selected by a random system data selection switch 2 by the output of a random system decoder 1, and is held at a serial output control circuit 6 via a random system output line RL. The data is outputted by the first clock phi after transferring the data. The counter circuit 11 loads an external address at the time of transferring the data, and sets the internal address at the address larger by one address than the external address, and also, increments a first internal address by a second clock phi. Also, the first clock phi after transferring the data is prohibited to be inputted to the counter circuit 11 by a serial clock control circuit 2.