JPS59186194A - Dynamic memory provided with refresh counter - Google Patents

Abstract

PURPOSE:To attain quickly and simply an operating test or the like of a refresh counter by resetting the refresh counter by means of an external control signal. CONSTITUTION:When a refresh request signal REF being at a low level at refresh request goes to a high level, a reset generating circuit 10 is activated and a reset signal is generated from the circuit 10. This reset signal resets the refresh counter 8 to bring it into the initial state. Thus, the refresh counter is reset without interrupting power supply at the operating test and margin test or the like, allowing to pwrform these tests simply and quickly.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to Refre 11. A counter for shopping? Regarding dynamic memory.

[Background technology]

Data to remember? In a dynamic RAM (Random Access Memory) in which information is stored in a capacitor with or without charge, a refresher is required to maintain the information charge in the memory cell at all times.

Conventionally, as such a refresh method, for example, the refresh counter ki is generated internally by internally generating an appropriate address signal @, based on a control signal from the outside, and once every 2 ms. There is a method for performing rotation and flashing.

However, since the output signal of the refresh counter cannot be taken out externally, it is necessary to test whether the refresh counter operates normally or not, and to test the operating margin to study the timing relationship of each signal to guarantee the refresh amount. In this case, it is not possible to directly check the operation of the refresh counter. Therefore, normally, a refresh signal etc. is supplied from the outside, the refresh counter is counted up, all addresses are changed, four rows of data are written to the memory cell, and then all of these are read out so that the expected information can be stored. Check the sound to see if it is written, and indirectly check the operation of the refresh counter? I try to do it.

By the way, in such a force test, an accurate test cannot be performed unless the setting state of the refresh counter is known. Moreover, in a dynamic memory, there is no means to know the static state of the refresh counter. Therefore, a method can be considered to estimate the general state Di of the refresh counter by utilizing the operation in which the refresh counter is reset by a reset signal generated when the power is turned on.

But in such a way from the refresh signal? After several times of loading, the static state of the refresh counter often becomes obsolete. On the other hand, with conventional dynamic memory, every time the test conditions change during the refresh counter operation test or operation margin test, it becomes obsolete. Off and refresh counter? Lise, I need to let you go. As a result, a disadvantage arises in that the test procedure becomes complicated and the time required for the test becomes long.

[Purpose of the invention]

This invention was made against the above-mentioned background. During an operation test or an operation margin test of the refresh counter, the power supply is turned off every time the test conditions become red and the refresh counter is restarted. I need to sort it out &<
L... Easily increase test procedures by kneading [and test time? Is it possible to shorten it? purpose.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A summary of representative inventions disclosed in this application is as follows.

In other words, the present invention resets the refresh counter based on an external control signal such as a refresh signal, a row address strobe signal, or a column address strobe signal supplied from outside the memory. 1. Is there a signal to clear the trick? By providing a signal generating circuit that generates a signal, it is possible to set the refresh counter to a predetermined initial state without turning off the power supply every time. Is the above purpose easy to guess?
It is something to be achieved.

This invention FM51 will be explained below with reference to the drawings.

〔Example〕

Is Figure 1 the invention? This is an example of an applied MOS-RAM as a dynamic memory.

As shown in the figure, 1 is a memory cell consisting of a capantor for storing information, a switch, and a MO8FET. This is a memory array arranged in a J-square shape.

Reference numeral 2 designates an address buffer circuit, and the address buffer circuit 2 receives an X-system address signal AXi and a Y-system address signal A, which are supplied in two parts from the outside, as well as internal address signals a, ay. l
X i,
X L, a3'i, and ayi are cut out and output.

3a, 3b, internal address signals 6xj, , aXi and a71, output from the address buffer circuit 2,
a3'l f Then, the corresponding word line and data line in the memory array 1? X decoder circuit and X decoder circuit to be selected.

Reference numeral 4 denotes a row address strobe signal (hereinafter referred to as RAS signal) and a column address strobe signal (hereinafter referred to as OAS signal) supplied from the outside.

This is an internal signal generating circuit that generates and outputs an appropriate internal control signal based on an external control signal such as a write enable signal (hereinafter referred to as a 'vza signal').

When the R A and El signals supplied from the outside fall from a high level to a low level, an internal control signal φ8 is formed in the internalization signal generating circuit 4 and output to the address bar . Then, the address buffer circuit 2 captures the address signal Ax1' and holds it internally.
Internal address signal axi, τ? Cut out and output. Subsequently, internal control signal φ8 is output from internal signal generating circuit 4 to X decoder circuit 3a. Then, the X decoder circuit 3a decodes the internal address signals aXi and aXi f and selects the word line ? corresponding to the address Ax? Bring it to the selection level.

On the other hand, following the fall of the RAS signal, the OA S
When the signal falls to the low level, first, the internal control signal φ is formed as M and φA, and the address amplifier 9. The signals are output to the F circuit 2 and the Y decoder circuit 3b, respectively. Then, address bar 1. F circuit 2 receives address signal Ayt.
k and internal address signals a71, a71 'i
Shadow formation, Y decoder circuit 3b decodes its output sound L7
, and its output causes memory array 1. Is the corresponding data line in J? Then, data is leaked from the memory cell located at the intersection with the word line selected by the X decoder circuit 3a, and the data is made writable.

Reference numeral 5 denotes a bladder extraction circuit consisting of a sense amplifier, etc., and this readout circuit 5 receives an internal control signal φ8? supplied from the internal signal generation circuit 4. ] 7, the data read out from the memory array 1 is amplified and sent to the output terminal via the output buffer 6a. Output to ul.

Further, in the 7-digit write circuit, this write circuit 7 receives an internal control signal φW? supplied from the internal signal generating circuit 4. In response, the X decoder circuit 3a at that time responds to the data supplied from the input terminal D1n via the input buffer 6bi.
Information is written in the form of charges to the memory cell selected by the Y decoder circuit 3b and the Y decoder circuit 3b.

The internal control signals φ8 and φa are of the form Iiy based on the WB signal supplied to the internal signal generating circuit 4 from the outside. Further, the output buffer 6a, input cover, and buffer 6b are also supplied with an internal control signal φ from the internal code generation circuit 4 at an appropriate timing. , φ□.

In this embodiment, a refresh counter 8 is used to generate a refresh address in response to an external refresh request, and an appropriate internal refresh is performed based on a refresh request signal (hereinafter referred to as RKF signal) supplied from the outside. Signal φ,. □ and φ,. fz k
an internal refresh signal generation circuit 9 that outputs an iL-type;
Although not particularly limited, a reset signal generating circuit 10 is used which generates and outputs eight reset signals φr for the refresh counter 8 based on the RKF signal, RAS signal and wm token.

When the REF signal supplied from the outside falls from high level to low level, internal refresh signal generation circuit 9
The internal refresh signal φr6f+ outputted from the address buffer circuit 2 is supplied to the address buffer circuit 2, and the taking in of the X-system address code AX is completely prohibited.

Also, following the internal refresh signal φ, the output ref
+ The applied internal refresh coefficient φref2 is at 777
The output signal of the refresh counter 8 at that time is supplied to the 977 circuit 2 and taken into the address buffer circuit 2 instead of the address signal Ax. Then, an internal address signal corresponding to the setting state of the refresh counter 8 is formed and outputted from the internal signal generating circuit 4 in approximately synchronization with the falling edge of the RAS signal. Bubbles are inserted and decoded. That is, when the R]1IfF signal is set to low level (when a refresh request is received), the word line corresponding to the setting state of the refresh counter 8 at that time is selected inside the memory. Then, when the word line is set to the selection level, M-g? Refreshing of memory cells containing '1' is automatically performed.

It should be noted that the internal refresh counter 8 registers internal refresh 2 after a while after the RKF signal falls. Internal refresh signal φr supplied from refresh signal generation circuit 9
The count is increasing by 8,2. Therefore, the RFiF signal at an appropriate timing? The output of the refresh counter 8 is made to be an address signal by the internal refresh 1 nosh signal φr6ft outputted from the internal refresh signal generation circuit 9.

Then, counter 8 automatically counts up each word line within 2ms. It is possible to select 'Ff-v' at least once for all 1799737 memory cells.

Furthermore, in this embodiment, even if the RBF signal is set to a low level, the Y-system address signal Ay1 is not inhibited from being taken into the AT777777 circuit 2. Therefore, after selecting the word line using the internal address signals aXi and aXi based on the output of the refresh counter 8,
If the Y-system address signal Ayi' is supplied, the refresh counter 8 will refresh, 1. It is possible to read and write 1-bit data using a host address and an external address A y t.

FIG. 2 shows one embodiment of the reset signal generating circuit 10. This circuit consists of drive MO8FE TQ, I connected in series between power supply voltage vcc and ground.
and an inverter IV consisting of a valve cylinder MO8FETQ2,
Three input MOS FETs Qs, Q4 are connected in parallel between the ground and the A-canode.

Q5 Tokonera's MO8FETO co-tracing drain co-current drain. It is constituted by a rectangular tube MO8FETQ6 connected between C and a NOR gate circuit GN that receives power from the MO8FETQ6.

So L7, the drive MO8FETQ of the notebook inverter V,
The RAS signal, which is an external control signal for the memory, is supplied to the gate of the NOR gate circuit GN, and each input MO8 of the NOR gate circuit GN
The above inverter I is connected to the gates of F11iTQ, 3 to Q5.
Inverted signal of RAS signal by V, RKF signal and WK
A number of names are provided for each.

In addition, each MO8FETQI constituting the circuit of the above embodiment
-Q6 is assumed to be formed into an n-channel type, although there are no particular restrictions thereon.

2j7+(B) is the lyse of the above embodiment, 1. Is this a logic table for a logic circuit that is a digital signal generation circuit? It shows. As is clear from this table, when the RAS@ signal is set to high level, by supplying the low level REP signal and the WE signal, the reset signal φr8 can be activated as shown in FIG. can be generated. This allows the refresh counter 8 to be reset to the initial state at any time without turning on the power supply.

Therefore, Refre 1. ．． The setting state of the counter 8 can be easily estimated.

Note that the internal control signal φ from the reset signal generation circuit 10
Based on r8, Refre1. Instead of resetting the refresh counter 8 to the output state k (0, 0, ...0), the output state of the refresh counter 8 is changed to (1
, 1, . . . 1) may be set or cleared.

Furthermore, although the RAS signal and the WZ flaw signal are directly supplied to the reset signal generating circuit 10, the present invention is not limited to this;
It is also possible to input a signal derived from an AS signal or a WE signal.

Next, FIG. 4 shows another embodiment of the reset signal generating circuit 10 described above.

The circuit of this embodiment has a Mo5FFiTQ+t which is operated by an internal control signal φ□ in phase with the RAS signal outputted from the internal signal generation circuit 4 in substantially synchronization with the fall of the RAEI signal, and a signal φ□ in phase arrest. It is equipped with a bush pull stage PPi consisting of Q10. In addition, there is a switch MOS FITQI3 that is turned on and off by the output signal of this bush pull stage PP, and this Nuivuchi MO8FETQ.
Is and two suis connected in series, Sochi MO8
7ETQ+4. .

The capacitor a, which is charged by Q+s, is provided at the front stage of a logic circuit composed of an inverter V and a three-power NOR gate circuit GN that receives its output, similar to FIG. 2 (A"l).

The control signal φ□ derived from the RAS signal and the refresh request signal RKF are supplied to the gate terminals of the switches MO8FBTQ, z and Q, +s, respectively, and the drive MOS F of the inverter V is supplied. Fi T
For the gate of Q, +, the above condensate→No°C1
The level φ of the connection node nl between the switch MO8FFiTQ+*IQ+5 and the switch MO8FFiTQ+*IQ+5 is applied.

In the above circuit, when the RAS signal is set to high level, the signal φ□ is set low and the signal φ□ is set high.
The output node of the bush-pull stage PP is brought to a low level, and MOEIFFiTQ,3 is cut off. He's talented.
At this time, if the RFiF signal is also at high level, the signal φ□ causes MO8FETQ, +4 to become REF' again.
MO8FF2TQ+5 are both turned on by the signal. Therefore, while both the RAS signal and the RFiF signal are high, the capacitor C1 is at the power supply voltage V. o4 is charged, the node n10 level is made high, and the output of inverter E2 is made low level. Moreover, node n
The level 1 remains high until the RAS signal is changed to low level and the switch MO8FETQ+3 is turned on.

Therefore, as shown in Fig. 5, when the RAS signal is high and the lower level j/L of REF and WE is selected, M
O8FI! tTQ, ~Q3 is turned off, the output of the NOR gate circuit GN is set to high level, and the reset coefficient φr8
is formed. Moreover, in this circuit, RFfF
Even if the RAS signal is set to high level before the signal is changed to high level, MO8FI! ! TQI! 1 is turned off, the capacitor O, cannot be charged, and the node DI
The levels are up to low level 1. Therefore, regardless of the WE flaw signal level, the reset coefficient φr may be incorrectly reset.
8 is output.

ζ et al., recent dynamic and V-RI RAMs use RKF signals? A function called OAS-before-RAS is provided in which refreshing is performed by causing the OAS signal to fall before the fall of the RAS signal υ without using it, but in the circuit of the embodiment shown in FIG. , by replacing the RBF signal with the 0AEI signal that changes in the same way as the R11iiF signal in FIG. 5, it is possible to generate the refresh counter reset signal φr6 in the same way.

[Effects] As explained above, the present invention provides a refresh request signal (RFliF), a row address strobe signal (Rp, s), or a column 7 drain signal supplied from outside the memory.
A signal generation circuit that resets or clears the refresh counter and sets it to a predetermined initial state based on an external control signal such as a strobe signal (OAS). Since this is provided, it is possible to set the refresh counter to its initial state from the outside without having to turn off the power supply. As a result, the setting state of the refresh counter can be easily estimated, and when performing an operation test or an operation margin test of the refresh counter, there is no need to turn on the power every time the test conditions change. This has the effect of simplifying the test procedure and reducing test time.

Is this invention made by Nagisa? Although the present invention has been specifically explained based on examples, the present invention is not limited to the above examples, and the gist thereof is not limited to the above examples. It goes without saying that various changes can be made without departing from the above.

For example, instead of generating the reset signal φr6'4 based on the RFiF signal, RAS signal, or WE flaw signal as in the embodiment, a dedicated terminal may be provided to generate the reset signal from the outside. If there is an external control signal other than the 0AEI signal, it is possible to use it to generate a reset signal.

[Brief explanation of drawings]

FIG. 1 shows the reflation according to the present invention, 1. An example of a dynamic memory with a counter for Show Puauku'J
flt diagram, Figure 2 (A) is a circuit diagram showing an example of a reset signal generation circuit, Figure 2 (CB) is the logical relationship between input and output in that circuit? The diagram shown in FIG. 3 shows the timing of each control signal in the memory of the above embodiment. The timing chart shown in Figure 4 is an example of the reset signal generation circuit. The circuit diagram shown in Figure 5 shows the timing of each control signal in the memory used in this case. FIG. 1...Memory array, 8...Reflash counter, 10...Reset signal generation circuit. 566

Claims (1)

[Claims] 1. Equipped with a refresh karantake that automatically counts up based on an external refresh request;
In a dynamic memory in which an internal address signal is formed based on the output signal of the refresh counter and memory cells are sequentially refreshed, the refresh counter is set to a predetermined value based on an external control signal supplied from the outside. A refresh counter characterized by being set to the initial state? Dynamic memory. 2. A device for forming an internal control signal that causes the refresh counter to be set to a predetermined initial state when the external control signal satisfies a predetermined input condition based on two or more external control signals supplied from the outside. A dynamic memory equipped with a refresh counter as claimed in claim 1, characterized in that a signal generating circuit is provided.