SU1325708A1 - Binary code-to-code with arbitrary less significant order - Google Patents

Abstract

The invention relates to computing and digital instrumentation and can be used to convert a code with a programmable relationship of result and reference number. The aim of the invention is to improve the accuracy and speed of the converter. The goal is achieved by those. that the converter containing the output counter 17, register 14, sum-, mat 13, the first block of constant memory 10, the binary counter 6, the first 7 and second 8 decoders, 1 pulse generator, the first 2 and second 16 And elements, entered the second block 11 of memory constants, buffer register 9, frequency divider 5, element NOT 15, driver 12 and trigger 3. Moreover, the outputs of blocks 10 and 11 of memory constants are connected to the inputs of adder 13, the overflow output of which is through elements HE 1 5 and 16 connected to the counting input of the output counter 17, the information input of which is It is connected with the output of the register 14. The address inputs of the memory blocks of constants 10 and 11 are connected to the output of the buffer register 9, and the output of the trigger 3 controls the senior address input of the first memory block 10 of the constants. 1 il. a (L

Description

The invention relates to digital computing, to digital measuring equipment and can be used to convert a code of a number in accordance with the programmed value of the ratio of the result and the original number.

The purpose of the invention is to improve the accuracy and speed of the converter.

The drawing shows a diagram of the code converter.

The converter contains 1 pulse generator, element 2, trigger 3, output 4 of converter, frequency divider 5, binary counter 6, decoder 7 and 8. buffer register 9 constant memory block 10, second constant memory block 11, driver 12 pulses, adder. 13, register 14, element 15, element 16, output counter 17, installation input 18, information input 19.

The converter works as follows.

In the initial state corresponding to the start of operation of the device, the code is recorded in the binary counter 6 of the record

most significant bits of the number being converted, this is the code entered into the high bits

the full code of the number to be converted is written into the buffer register 9, register 14 and output counter 17 are set to the initial — zero state. Shaper 12 in the initial state of the forg-ing by the second frequency divider 5

generates a write signal to the lower bits of the counter 17 and controls the operation of the Pulse Generator 1. The trigger 3, when the initial state is set by a signal at input 18, is brought to the one state, in which the frequency divider 5 is kept in the zero state. At the same time, the signal at the first output of the decoder 8, affecting the first constant memory unit 10, turns the specified block into an active state, while the second block 11 is in the third state (the outputs are in high-impedance state)

When the generator pulses through the open element And 2 to the input of the binary counter 6, the consecutive subtraction from the counter contents occurs before the loan signal appears at the output of the decoder 7. The output pulse of the latter writes a zero to trigger 3, which causes the divider to unlock 5 frequencies.

In the course of work on subtracting the binary counter 6 with each subtracted pulse arriving at the input of the binary counter 6, the whole part of the low-order bit of the binary counter 6 is summed with the help of adder 13, register: 14, element 15, element 16 and output counter 17. In this case, the register 14 is triggered by the differential logical levels of the signal at the synchronization input. The transfer signal from the output of the adder 13 through the element is NOT 15 and the element And 16

It is transmitted to the summing input of the higher bits of the output counter 17. The lower half of the binary counter 6 is outputted as a corresponding code to the output of the first block 10

and in a tetraenie all the time the trigger 3 is in a single state. After the trigger 3 is set, the output pulse of the decoder 7 to the zero state changes the address at the input

the first block 10 and its output receives a code corresponding to the product of the number entered in binary counter 6 and the fractional part of the low-order bit weight of the specified counter. With

the buffer register 9 (and in the binary counter 6) is the address of the corresponding product in the first memory device 10. When the condition of the decoder 8 on the second output is reached, the second unit 11 is switched to the active state during one 40 time off (transfer of block 10 to the third state). To the address inputs of the second block 1 1, the code of the lower bits of the number to be converted is fed. The output of block 11 is given a code corresponding to the product of the weight of the lowest bit of the code being converted by the number represented in the specified lower bits.

gQ Thus, in the process of code conversion, sequential reading of information from blocks and summation with accumulation of the result in the output counter occur. The transfers occurring in the adder 13 are taken into account by summing these transfers in the form of counting pulses, coming through the element 15 opened by the transfer signal, the element 15

And 16 to the summing counting input of the higher bits of the counter. In the output counter 17 at the end of the operation of the device: a transformed

The code that is outputted to output 4. The conversion ends at the moment the frequency divider 5 switches from the state in which the second output of the decoder 8 is excited to the next state. At the same time, by the signal differential at the first input of the imager 12, a single signal is output to its output, which, having entered the pulse generator 1, blocks the output of clock pulses, since the younger part of the counter 17 is in recording mode during the conversion, then the state of the register 14 is trans. written to the corresponding bits of the counter 17. The next conversion cycle begins after the arrival of the next pulse at the input 18 of the initial state setting.

The structure of the proposed converter allows, by expanding the number of outputs of the decoder 8 and the corresponding number of constant memory blocks, to increase the partitioning of the output counter. The presence of countable chips in the low-order bits of output counter 17 allows one to receive an additional correction to the number-pulse code from an independent source.

Example. Let the ratio of the low-order bits to the result of the conversion and the input code be 0.3346652, and the number to be converted is represented by the 16-bit binary code. In the first block of 10 memory constants, the weights of the lower bits of the binary counter 6 are stored. On the basis of the available element base of memory devices (556PT7 chips) with the organization 2048x8, choose the variant with the 8-bit adder 13. Determine the maximum number of lower-order bits of the input code that can be converted directly in the second memory block 11.

The maximum number, whose code, taking into account the eight output bits of the memory block, can be directly

use ° as 1dress in the second memory block 11, the number code is 761.95553. This number corresponds to nine bits of the binary code being converted, since

ten

15

20

-,

45

325708

The bone of ten bits is 1024. Thus, the nine minor bits of the input code recorded in buffer register 9 are converted into code with a new bit weight directly using the second memory block 11.

The remaining seven most significant bits of the code to be converted are also written to the buffer register 9 and addressed to the first memory block 10. The low bit weight of the binary row counter 6 is determined, into which the upper seven bits of the code to be converted are also written. In the convertible code, this bit is the tenth, i.e. It has a weight of 512 units of low-order convertible code. Taking into account the required ratio of the weights of the conversion result and the source code, the weight of the lower bit of the binary counter 6 is equal to 171.34858. In the first block of 10 memory, the code 25 of the number 171 is entered into all the cells corresponding to the unit state of the trigger 3.- During the process of subtracting from the contents of the binary counter 6, the numbers 171 are summed as many times as the initial code entered into the counter 6 . multiplication occurs by 171 and the result is fixed in the counter 17 of the result. When the trigger 3 is set to the zero state, one of the products enters the output of the first memory device.

thirty

35

P . N = 0.34858,

where P is the work;

N- is the number represented in

the upper seven bits of the code being converted (the maximum value is N "ax 127; 0.34858 is a fractional part of the weight of the lower bit of the senior seven bits of the number being converted.

For the maximum number at the output of the first storage device 10, the code of the integer part of the number is formed, equal to 44.26966.

The fractional part is thus dropped and enters into the error of transformation.

From the example we see that the maximum. the error value in the proposed device will not exceed two units of the least significant bit of the conversion result that occurs during selection

syvanin of fractional parts for the numbers represented in the first block 10. (with the zero state of trigger 3), as well as for the numbers represented in the second memory block. The conversion time is NIN in the proposed device when

a frequency of 1 MHz is about 130 µs

/

Claims (1)

Invention Formula Binary code to arbitrary low bit weight code converter, containing a decoder counter, register, adder, first constant memory block, binary counter, first and second decoders, pulse generator, first and second And elements, the first inputs of which are connected to the output of the generator pulses, the discharge of the adder output is connected to the information input of the register, the output of which is connected to the first input of the adder, the output of the first element I is connected to the counting input of the Binary counter, the output of which is connected to the input of The first decoder, the output of the output counter is the output of the converter, the installation input of which is connected to the reset inputs of the output counter, binary counter and pb histra, characterized in that, in order to improve accuracy and speed, a second block of memory constants is inserted into it, a buffer register , frequency divider, pulse shaper, NOT element and trigger) whose installation input is Editor V. Bobkov Compiled by N. Shelobanova Tehred I.Popovich Proofreader V. But ha Order 3125/56 Circulation 901 Subscription VPIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 dinene with the converter installation input and the reset inputs of the Pulse generator and the buffer register, the outputs of which are connected to the address inputs of the first and second constant memory blocks, the output control inputs of which are connected respectively to the first and second outputs of the second decoder, the input of which is connected to the output of the frequency divider, the information input of which is connected to the output of the pulse generator, with clock inputs of the register and the first decoder, the outputs of which are respectively connected to the information input s of the output counter and the reset input of the trigger, the output of which is connected to the control input of the frequency divider, the second input of the first element And and. the input of the high bit of the address of the first memory block of constants, the output of which is connected to the second input of the adder and the output of the second memory block of constants, the transfer output of the adder through the element is NOT connected to the second input of the second element And whose output is connected to the counting input of the output counter, input the recording of which is connected to the output of the imager, the control input of which is connected to the second output of the decoder, and the output of the imager is connected to the control input of the pulse generator, the information input of the converter dinene with information inputs of a binary counter and buffer register.