SU453662A1 - - Google Patents

Description

one

The invention is intended to be used as a secondary standard of time, as well as single time systems in various areas of spiders and technology.

Known electronic clocks built in counting decades with feedback have insufficient accuracy and are complicated due to the large amount of equipment.

To simplify and improve the case in the proposed clock, a timing circuit is made on memory elements combined into a matrix having read and write read generators, the input of the number register is connected to a quartz oscillator, and the output of the number register is connected to indicators of counted time units.

The drawing shows a block diagram of the proposed hours.

The clock contains master clock 1, decade 2 and 3 frequency divider, decoder 4 and 5, assembly OR 6, trigger 7, number overflow register 8, keys 9, 10 and 11, trigger 12, matrix 13 buses, read and write generator 14 , amplifiers 15, assembly “OR 16, key 17, lamp drive 18, digital indicator lamps 19 and key drive system 20.

The clock works as follows.

Quartz oscillator 1 produces two pulse sequences with a frequency F and

shifted in relation to each other by 1/2 of the repetition rate. The pulses of the generator are fed to the input of the first decade 2, which divides the repetition frequency of pulses by ten.

The state of the four triggers of the first decade 2 is decoded by the decoder 4 having ten outputs. The overflow pulses of the first decade 2, following with the frequency-, are fed to the input of the decade 3 frequency divider. The state of the triggers of decade 3 is decoded by a decrypter of 5 states having ten

exits. The outputs of the decoder 5, controlling the key 17 and the generator 14, alternately read and write the storage tetrad matrices into the register of the 8th number, simultaneously changing the conversion factor to

according to the number of the tetrad, the overflow pulse of decade 3 through the assembly "OR 6 is stored in the trigger 7 of the intermediate memory and, after reading the lower tetrad of the matrix 13, is fed through the key 9, controlled by the output of the decoder 4, pa the counting input of the register 8.

The impulse from the output of decade 3 resets

trigger 7, and the outputs of the decoder 4, control

Key 10 sample bits together with

selection keys, generators 14 records and

With the prohibition keys AND, one writes a new record of the contents of the register of the 8th number to the corresponding memory tetrad. The overflow signal of the 8th register is stored in the trigger of the intermediate memory 7 and is added to the 8th register after reading the next storage tetrad of the matrix 13.

Determination of the state of the register 8 triggers and the selection of the required cathode of the indicator lamp by the number of debris and key drive system for the lamps 18 on the cathode side are made after reading and adding one and continue until the register triggers are reset by trigger 12.

Subject invention

An electronic clock containing a quartz oscillating master oscillator, a two-decade frequency divider, time counting, control and indication of the counting time, characterized in that, in order to simplify and increase reliability, the time counting circuit is implemented on memory elements combined into a matrix having The read and inhibit readout generator, in which the input of the number register is connected to a quartz oscillator, and the output of the number register is connected to the indicators of the time units to be counted.