RU1772890C - Generator-frequency meter - Google Patents

Abstract

The invention relates to a pulse technique and can be used to increase the reliability and expand the functionality of a frequency generator. The object of the invention is achieved by introducing an AND-OR-NOT 4 element (2N), an annular counter 6, and new functional connections. In addition, the device comprises a clock frequency generator 1, a group of frequency dividers 2.1-2.N-1, a shaper 5 time intervals, a counter 7, a register 8, a decoder 9 and a group of indication elements 10.1-10, N. Improving reliability and expanding functionality due to the ability to measure the frequency of generated oscillations in the smooth tuning mode of block 1 is provided by using a counter 7, register 8 and a decoder 9 for sequential dynamic indication of the digits of the measurement result, the codes of which are generated as residues from the division of a fixed time interval for periods of reference frequencies, 1 ill. 31 3.2 VJ VI YU 00 8

Description

The invention relates to pulsed technology and can be used in measurement technology to generate frequency-tunable pulse signals with an indication of the generated purity.

The aim of the invention is to increase reliability and expand functionality by tuning the frequency of the generated signal,

The drawing shows a functional diagram of a frequency generator.

The device comprises a clock generator 1, a group of dividers 2.1-2. (N-1) frequencies, a group of output buses 3.1-3.N, an element (2N) AND-OR-NOT 4, a shaper 5 time intervals, a ring counter 6 , counter 7, register 8, decoder 9 and a group of indication elements 10.1-10.N.

The output of the clock generator 1 is connected to the input of the series-connected dividers 2.1 -2. (M-1) frequencies, the outputs of which and the input of the first frequency divider 2.1 are connected respectively to the first group of inputs of the element (2N) AND-OR-NOT 4 and form a group of 3.1-3.N device output buses. The output of the last frequency divider 2. (N-1) is connected to the input of the driver 5 time intervals, the output of which is connected to the clock input of the register 8, the reset input of the counter 7 and to the counting input of the ring counter 6, the outputs of which are connected respectively to the second group of inputs of the element (2N ) AND-OR-NOT 4, the output of which is connected to the counting input of the counter 7, the outputs of which are connected to the information inputs of the register 8, the outputs of which are connected to the inputs of the decoder 9, the outputs of which are connected to the information inputs of each of N elements group elements 10.1-10.N display indication. The outputs of the ring counter 6 are connected respectively to the control inputs of the display elements of group 10.1-10.N of the display elements.

The device operates as follows,

The clock generator 1 generates rectangular tunable pulses within the range of F ... 10F, which, after dividing by the frequency in the group of dividers 2.1-2. (N-1), the frequencies go to the group 3.1-3.N of the output buses of the device. The output pulse of the last divider 2. (N-1) frequency starts the shaper 5 time intervals, duration

whose momentum is equal to

- AT

as a result, even with a maximum frequency of generator 1 equal to 10F, the duration of the specified pulse does not exceed the period of the start signal at the input of block 5.

On the front of the output pulse of the shaper for 5 time intervals, the ring counter b is set to the next state, which opens the next AND element in the group of elements forming the AND-OR-NOT 4 element (2M) and turns on the next indication element of the group of 10.110 .N indication elements. As a result, the next bit of the result of the frequency measurement is displayed and simultaneously in the counter 7 under the action of the outputs coming to its counting input

element (2M) AND-OR-NOT 4 counting pulses from the next output of the group of dividers 2.1-2. (N-1) frequency the binary code of the digit of the digit displayed at the next iteration is generated. This code is on the back

to the front of the output pulse of the shaper, 5 time intervals are recorded in the register 8 and then, after decryption in the decoder 9, the group of indication elements 10.1-10.N is input. At the same time, the counter 7 is reset to the initial state along the trailing edge of the output pulse of block 5.

Thus, the result is displayed in the device, each of the bits of which is calculated as the remainder of the division of the duration of the counting interval by the duration of the counting pulses. When the counter 7 is selected in decimal and the division factors of divisors 2.1-2 (N-1) equal to 10, the result of the frequency measurement is also displayed in indicators in decimal form.

The proposed device, in comparison with the prototype device, has increased reliability by reducing the number of registers and decoders, and, unlike the prototype device, it allows measuring the frequency during smooth tuning of the clock frequency generator 1.

Claims (1)

45 claims The frequency generator, containing a serially connected clock generator and a group of N-1 frequency dividers, the outputs of which form the output bus 50 of the device, a time interval shaper, counter, register, decoder and a group of N indication channels, output (1M-1) - the frequency divider is connected to the input of the shaper 55 intervals, the output of which is connected to the register clock input and to the counter reset input, the outputs of which are connected to the information inputs of the register, the outputs of which are connected to the decoder inputs, the outputs of which are connected to the information to the input inputs of each of the N frequency elements, the output of the shaper of time indications, characterized in that, at certain intervals, it is connected to the counting input in order to increase reliability and expand. a ring counter, whose outputs of neither functionality are connected to the second group of inputs of the frequency tuning element of the generated signal-5 ta (2N) AND-OR-NOT, the output of which is connected, a ring counter is inserted into it and elec- tric to the counting input counter, outputs ment (2M) AND-OR-NOT, the first group of inputs of the ring counter connected to the control - which is connected to the outputs of the generator inputs of the display elements of the clock group and the group of (N-1) divide-from N display elements.