SU1622917A1 - Digital multiplier of recurrence rate of intermittent pulses - Google Patents

Abstract

The invention relates to radio engineering and digital measurement technology and can be used to convert periodic signals in meters and frequency converters with a small discretization error. The purpose of the invention is the elimination of false frequency samples when the input signal disappears. The frequency multiplier includes a pulse former 1, a frequency divider 3, a variable divider 4 frequencies with a variable division factor, a register 5 and a pulse counter 7. Element II is introduced into the multiplier. Memory code memory block 6 and code comparison block 8. The combination of newly introduced elements and connections prevents the appearance of a high frequency of pulses when the signal at its input disappears. 1 il.

Description

The invention relates to radio engineering and digital measuring equipment and can be used to convert periodic signals in meters and frequency converters with a small 5 discrete error.

The aim of the invention is the elimination of false samples of the frequency when the input signal disappears.

The drawing shows a structural 10 electrical circuit of a digital frequency multiplier repetition of periodic pulses.

The periodic pulse repetition frequency multiplier comprises a pulse generator 1, element I 2, a frequency divider 3, a frequency divider 4 with a variable division coefficient, register 5, a reference code memory unit 6, a pulse counter 7, and a code comparison unit 8. 20

The multiplier works as follows.

In the initial state, the signal at the output of block 8 corresponds to the logical one, therefore, the And 2 element is opened by this signal at the second input 25, and the pulses of the fixed reference frequency F _O n pass through the And 2 element to the input of the divider 3 and the counting input of the divider 4. At the output of the divider 3 pulses are formed with a frequency of F _O n / N. where N-30 is the division coefficient of the divider 3, which are received at the counting input of the counter 7.

With the multiplier input to the control input of register 5 and the generator 1 is input a periodic sequence of pulses 35 NOSTA frequency F _BX. For a given edge of each input pulse, the shaper 1 generates a short pulse, which resets the counter 7. After zeroing, the counter 7 starts to fill up with the pulse 40 themselves, coming in from the output of the divider 3. By the arrival of the next input pulse at the outputs of the counter 7, a code number n equal to the ratio frequency F _O n / N filling counter 7, and input F _BX frequency 45 _ 'fpn

Fbx N

The code of this number is written into the register 50 by the input pulse and arrives from its outputs to the control inputs of the divider 4, then the output pulse of the shaper 8 again resets the counter 7 and the cycle repeats. In this case, the divider 4 divides the clock frequency Fon by the number n, and at its output, and therefore, at the output of the device, pulses with a frequency F _B wx <equal to

Thus, the frequency F _Bb i _X pulses at the output of the device is N times higher than the frequency F _BX pulses at its input.

The memory block 6, block 8 and the And 2 element prevent the presence of false frequencies at the output of the multiplier when the input signal disappears. This is as follows.

In block 6 of the memory code is written number

Omake -

F optT max N where T ^{max_ is the} maximum possible period of the input pulses. The code of this number goes to the first group of inputs of block 8. After the lapse of the input signal of the time interval ί = T max + N / F _on , the Omake code appears on the outputs of the counter 7 and the second group of inputs of block 8. Block 8 when the codes are equal on the first and the second group of its inputs generates a logic 0 signal. This signal is fed to the second input of the And 2 element, as a result of which the And 2 element is closed at the second input, and the reference frequency pulses cease to go to the counting inputs of the counter 7 and the divider 4, therefore, disappear and pulses and the output device.

When the pulse signal appears again on the input bus of the multiplier, the counter 7 is reset to zero, the logical 1 signal appears at the output of block 8. The And 2 element opens at the second input and the device resumes operation.

Claims (1)

Claim A digital pulse repetition frequency multiplier consisting of a series-connected divider, counter, register and divider with a variable division coefficient, as well as a pulse shaper, the pulse shaper output being connected to the counter zeroing input, the register recording input combined with the pulse shaper input and being an input multiplied frequency, and the inputs of the divider are combined and are the input of the reference frequency, characterized in that, in order to eliminate false readings of the frequency in the disappearance input signal, a reference code memory block, a code comparison block, the first group of inputs of which are connected to the outputs of the reference code memory block, and the second - with the outputs of the bits of the pulse counter, and the element And, the divider inputs are connected to the reference frequency input through the And element, the second input of which is connected to the output of the code comparison unit.