SU1314435A1 - Digital frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to improve frequency multiplication accuracy. The device contains a reference oscillator, a divider 2 frequencies with a variable division coefficient, a memory register 3, a divider frequency 4, two counters 5 and 7, a pulse shaper 6 and a reversible counter 8. The goal is achieved by introducing counters 7 and 8 that change per unit binary code at the output of the register 3. 1 Il. sl with: 4 4 WITH SL

Description

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The invention relates to radio engineering and communications and can be used in measurement technology.

The purpose of the invention is to increase the frequency multiplication accuracy.

The drawing shows a structural electrical circuit of a digital frequency multiplier.,

The digital frequency multiplier contains o / 1o-p v1y.gener; ator 1 ,, divider 2 frequencies with a nominal division factor, register .3 and mi, divider A frequencies, count 5 ,. shaper 6 pulses, additional 7 and reversing 8 sch) etchiki about

Digital frequency multiplier works as follows.

The input of the imaging unit 6 receives a sequence (with a frequency Fg) of short pulses, the front of which records information from the bit outputs of counter 5 to register 3 with the addition of one and sets the initial state of the reversible counter 8, and the pulses at the output of the imager 6 produces a short pulse, which sets the divider 4, the counter 5 and the divider 2 frequencies with a variable division factor to zero and arrives at the output of the digital frequency multiplier. The periods of the input signal are measured using reference oscillator 1, divider 4, counter 5, and additional counter 7. If the division factor of divider 4 is K, then the binary code on the bit outputs

of the counter 5 varies with the frequency F / K (where F0 is the frequency of the reference oscillator 1). At the end of the input signal period, the binary code of the number N Fp / Fg is set to K on the bit outputs of the counter 5, and on the bit outputs of the additional counter 7 the binary code can take the values of О ЛК i К, On the front of the input signal В the register 3 writes the code of the number H + 1, and the reversible counter 8 is set to the state corresponding to the binary code of the number K.

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At the output of the separator 2 frequencies with a variable division factor, pulses are formed with a frequency F, „

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 Fp / (N + 1). After the arrival of dK 5 pulses from the output of divider 2 frequency with a variable division factor on the subtracting input of the reversible counter 8, a pulse is generated at its output, which goes to the subtractive input of register 3, the binary code at its output changes by one, and the pulse frequency the output of the divider 2 frequency with a variable division factor takes the value Fg; ,, FU / X. Pulse frequency at the output of the digital frequency multiplier Rd. ,, RY

Claims (1)

Invention Formula o " five 0 five 0 A digital frequency multiplier containing a series-connected reference oscillator, a frequency divider, a counter, a memory register and a frequency divider with a variable division factor, the counting input of which is connected to the output of the reference oscillator, a pulse shaper, the output of which is connected to the initial setup input of the counter, and the input of the forwarder pulses are combined with the memory register write input, which differs so that, in order to improve the frequency multiplication accuracy, additional connected serial numbers are introduced tchik and reversive counter, V5SOD initial installation of which. It is combined with the input of the pulse generator, the reverse count input of the reversible counter is connected to the output of a frequency divider - with a variable division factor, the input of the initial installation of which is combined with the initial installation input of the frequency divider and connected to the output of the pulse former, the output of the reference generator is connected to the counting input of an additional counter The input of the zero setting is combined with the counting input of the counter, the output of the reversible counter is connected to the subtracting input of the memory register.