SU677095A1 - Number code- to-pulse recurrence frequency converter - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used in frequency-digital devices and as a store of frequencies in measurement technology.

A known converter of a code of a number into a pulse following frequency, comprising a pulse generator, a frequency divider, counters, and an integrator 1.

However, this device has insufficient accuracy of conversion.

A known converter of a code of a number into a pulse following frequency is contained, comprising counters, a comparison unit, and pulse generators 2.

The purpose of the invention is to improve the accuracy of the conversion.

The goal is achieved by the fact that a number-to-pulse-to-pulse code converter, containing a series-connected pulse generator, a frequency divider, the first AND element and a pulse counter, as well as a control trigger, the output of which is connected to the second input of the first And element and connected to the input an output of a controlled frequency divider, a return count counter, the input of which is connected via the second element I to the output of the pulse generator, and a comparison unit whose inputs are connected respectively to the outputs of a return counter and pulse counter, the output of the comparison unit is connected to the second pulse counter input directly, and through the inverter is connected to the output busbar, a summing counter, a second comparison unit, a number code register, a numeric control register and a control trigger, as well as a read unit are added. Chpsovoy

the register is connected to the input of a summing counter through a readout unit, the second comparison unit is connected to the outputs of the number code register and the high-order bits of the adding counter, respectively.

The output of the comparator unit is connected to the second input of the second element AND and the first input of the secondary control trigger. The output of the additional control trngger is connected to the third input of the second element I. The second input of the additional control trigger is connected to the input of the numeric register, and the second input of the reading unit is connected to the output of the second element I.

Pa figs. 1 shows the electrical circuit diagram for converting a code of a number to a pulse frequency; in fig. 2, a - and given time diagrams. Number to frequency converter

pulse following contains elements

And 1, 2, inverter 3, comparison unit 4, generator 5, pulses counting 6, controlled frequency divider 7, number code register 8, numeric register 9, additional control trigger 10, control trigger II and input buses 12, 13, 14 of which are first connected to the register 8 input of the number code, the second to the input of the numeric register 9 and the first input of the additional trigger 10, a third to one of the inputs of the control trigger 11 and the local reset bus 15, the counter 16 inverse values, readout block 17, the summing counter 18, the second block 18 of the comparison and the output hydrochloric bus 20.

FIG. Figure 2a shows the pulses o6pani.e. to the converter arriving over time ti. With the arrival of the inverter, all the memory elements of the converter are zeroed out during time 4, and unit voltage levels are set on the forward shoulders of the inverse counter triggers.

On bus 12, the number code .V is entered into register 8 of the number code according to the condition of the problem (L is the maximum number of pulses that must be received at the output of the converter during a conversion cycle 4). The number of bits in register 8 of the number code is selected by a certain number of chips more than the number N determined by the required accuracy imposed on the uniform distribution of the pulses in the conversion peak (Fig. 2e, t).

On bus 13, the current parameter code, for example, speed increment, acceleration, etc., is written to the numeric register.

The code can take consecutive values from 000 ... O to 111 ... 1, i.e., to the maximum code of the number N (Fig. 2.6).

The code in the numeric register is entered on the basis of an incoming gating pulse (Fig. 2, s), which is fed to the first input of the additional control trigger 10, the latter changes its state, and its output signal permits the passage of pulses from the generator 5 pulses to the input counter 16 reverse values through the element And 2 and at the same time on one of the inputs of the block 17 read.

With each pulse, the information of the numeric register 9 is read by a parallel code into the lower bits of the adding counter 18. The code comparison unit 19 compares the number of the senior bits of the 1, its counter 18 with the number in the 8 code of the number code. At the moment of equality of the numbers recorded in the summing counter 18 and the 8 code number register 8, the code matching unit 19 generates a signal that simultaneously enters the input of the AND 2 element and the second input of the additional control trigger 10, which changes its state, and the signal from its output prohibits the arrival of pulses in the counter 16 and the reading block 17.

The number recorded in the counter of inverse values determines the recalculation coefficient of the pulse count 6 per unit less, since the initial state of the counter of inverse values is taken as one.

A sign of the start of a conversion cycle is a pulse coming through the bus 14

to the trigger control input 10 (Fig. 2, d), which changes its state, and the signal from its output (Fig. 2, e) allows the arrival of pulses from the controlled frequency divider 7 and the input of the counter 6 pulses and

simultaneously to the input of block 4 comparison.

At that moment, when the logical product of the inputs of the coping unit 4 becomes equal to one and the next input signal comes from the controlled frequency divider 7, from its output a pulse arrives at the installation inputs of the trigger 211-21 "of the pulse counter 6 and resets it to its original state the At the same time, this impulse through the inverter 3 is fed to the bus 20 at the output of the converter.

Since the pulses to the input of the counter arrive continuously during the conversion cycle (Fig. 2, e), each time

After resetting the pulse counter 6, it starts counting the pulses again, and the process repeats.

After the controlled frequency divider 7 counts the number of pulses equal to the number L recorded in the 8 code code register 8, its output is formed, according to which the control trigger 11 returns to the outgoing state, and the other elements are reset to zero on the local reset bus 15 memory converter.

Thus, the number of pulses, equal to the number recorded in the numeric register 9, arrives at the output 20 of the converter. The occurrence of the first output pulse and the intervals between the output pulses are determined by the code of the number recorded in the reciprocal counter and the frequency of the controlled divider 7.

The frequency of the controlled divider is determined by

1 t

j

G „

affairs

where is the pulse repetition rate from the controlled frequency divider; TO is the period of formation of a single pulse in a conversion cycle;

t-cycle time conversion; N is the maximum number of pulses at the output of the converter, which is known from the condition of the problem.

With the decimal code four, written in the numeric register 9 (Fig. 2, g), only four pulses are received at the output of the converter, uniformly distributed in the conversion cycle t, (Fig. 2.5).

FIG. 2, 3, and the distribution of impulses at the output of the converter is shown in the case when the code of an odd decimal number 5 and a code corresponding to the number N equal to 24 are written in the number register.

Claims (2)

1. Japanese Patent No. 49-21824, 98 (5) p. 04/31/69. 2. USSR author's certificate number 449444, cl. N OZK 13/02, 25.09.72.