SU999048A1 - Unit counting squaring converter - Google Patents

Description

(54) NUMBER - PULSED SQUARE CONVERTER

   -- one .-

The invention relates to computational and pulsed techniques, is intended to convert the number of pulses into a binary code of the square of the number of pulses, and can be used in functional information input devices. -. . . .: . .. - -

Known Converter, providing a binary output. Eod, proportional to the square of the number of pulses arriving at the inputs, with {Holding two counters, a group of elements And and a chain of successively connected delay elements. In this case, the inputs of the chain of delay elements in the first counter are combined. The outputs of the bits of the first counter through the elements And are connected to the corresponding bits of the second counter. The second inputs of the And elements are connected to the corresponding outputs of the chain of delay elements Cll.

A disadvantage of the known device is the complexity of the design.

The closest to the invention in its technical essence is a device containing a key, first and second binary counters, the first of which is connected to the output% (key, group of delay elements, group of elements I. At the same time, the single outputs of the bits of the first counter are connected to the first inputs of the element I, the second chops of which are connected to the input, the devices through delay elements.The counting input of the second binary counter is connected directly to the input of the device.The counting inputs of the second trigger C4etv.chika are connected to the outputs cops and C23.

A disadvantage of the known device is the increased amount of hardware costs.

The aim of the invention is to simplify the converter by reducing the equipment used.

The goal is achieved by the fact that in a numerical quadratic 3 converter containing two counters, a key, a group of delay elements, a group of elements AND, and an element AND, the input of the clock pulses of the converter is connected to the information input of the key, the output of which is connected to the input of the first delay element groups, output i - i, i 1,2. . . . the group delay element (where i is the number of bits of the first counter) is connected to the input of the (i + 1) th group delay element and the first input of the i - group AND element, the second input of which is connected to the output of the i-th bit of the first counter , the output of the i-th element of the AND group is connected to the counting input of the i-th bit of the second counter, contains two series-connected flip-flops, and the key output is connected to the counting input of the first bit of the second counter, the output of the second bit of which is connected via a delay element to the counting input first account sensor, the input clock of the converter is connected to the input of the first trigger, the output of which is connected to the first input of the element And the output of the first discharge of the result of the converter, the outputs of the second and third discharge of which are connected respectively to the bus of the zero potential of the converter and the output of the element And, the second input of which connected to the output of the second trigger and the control input of the key, the converter inputs, starting from the fourth, are the outputs of the second counter. The drawing shows a block diagram of the converter. Number - pulse quadratic converter contains key 1, trigger 2; key, the element And 3 key, counters 4 and 5, a group of 6 delay elements, a group of 7 elements And, the element And 8 and the element 9 delay, triggers 1O and 11. The converter works as follows. Using two triggers Yu and 11 and element 8, the corresponding conversion of odd and even pulses is performed according to the table (it is easy to see that for any pulse numbers, the 2nd bit of the output code of the square of numbers will always be zero). S Square Calculation Algorithm Has A + B + C, P o or. O, if P is an odd number; (2) 1, if 4, if (Hereinafter, the operation j-f.cooTBeTCTset the integer part of a number). B, 8 i: (P-2), length (3), C 8, E1 for P, 7..4). From the described transformation algorithm, taking into account (2) - (4), it can be seen that the terms in (1) A, BIS are calculated simultaneously. Before starting, the initial state (input of the initial installation is not shown), trigger 2 of key 1, triggers 10 and 11, and counters 4 and 5 are set. The first counting pulse applied to the input of the converter transfers the single state of trigger Y. At. By this, the key 1 input is blocked by the trigger 2 output. At the moment the second counting impulse arrives, the trigger 10 returns the initial state to B and the second trigger 11 is triggered. As a result, the potentials ensuring the presence of a logical unit at its output are triggered at the output of the And 8 element. The potential difference at the output of the second trigger 11 triggers trigger 2 and permits the passage of counting pulses through key 1. Thus, key 1 now allows all counting pulses to arrive at the same time at the first discharge input of counter 5 and to the input of the series 6 delay elements . The delayed counting pulse does not pass through the elements 7, since their control inputs are blocked by the bits of the counter 4, It is easy to see that the two triggers 10 and 11 operate essentially in the frequency division mode, they work similarly until the seventh counting pulse and the first two triggers of the lower bits of counter 5. The sixth counting pulse generates a transfer signal at the output of the second trigger of counter 5, which through delay element 9 arrives at the counter input of the first discharge trigger of counter 4 and sets e therefore, it permits the arrival of the counting pulse delayed by element 6 to input 5, the seventh counting pulse simultaneously arriving at the input of the first trigger 10 and the input of the counter 5, passing through the electric amp; Delay moment 6, through element And 7 re-enters the input of counter 5. Since until the seventh pulse arrives at the input of counter 5, four pulses are received through key 1, they will be five at the moment of the seventh pulse, the sixth will come from the element output 7. Thus, five counting pulses came from the input of the device through key 1, and the circuit came from the delayed element 6 and element 7, the control input of which was opened by a signal from the output of the first discharge trigger of the counter 4. It’s easy to see how and seventh, afterwards Three counting pulses enter the input of the third trigger of counter 5 twice: directly at the moment of each arrival at the input of the converter and with a delay through said chain delay element 6, (- element 7. At the moment of the tenth counting pulse at the input of the converter (the eighth - at the input of the counter 5) at: the output of the second trigger of the counter 5, the transfer signal is re-generated (like the first time by the sixth) to the fourth - at the input of the counter 5 (counting pulse), which is through element 9. the delay arrives at the input of the first discharge trigger of counter 4. Thus, counter 4 records the code of the number two, i.e., the trigger of the second discharge of counter 4 is now in the unit state and resolves the arrival of the delayed a pulse to the input of the second trigger of counter 5. Therefore, the number recorded in counter 4 is added to the number of pulses received at the input of counter 5 with a delay determined by a group of delay elements. In counter 4, the number code is increased by one by A Promoted Quartet of counting pulses, starting with the most generous, from the number of converters arriving at the input. Counter code 4 determines the number of delayed pulses to be added to the corresponding bits of counter 5. The number of pulses that are fed to the input of counter 4 during the arrival time of the input of the X number of counting pulses can be written OR OR 2%. At the same time, A binary counter can be written as mc.x 42j44 "I-2- (f) K2X. It is not difficult to see that in a known device that squares the maximum number X 2 - 1 counting pulses, the output counter is 2. Discharge ness of another binary A counting device that provides counting of numbers, excluding the first counting pulse, is equal to c. The proposed device requires less equipment than the known device, and the smaller the number of bits, the greater the gain. Comparison of the characteristics of these devices in terms of the number of equipment gives the following winning 3 13, where c is the width of the argument, it is believed that the counting trigger on equipment is equivalent to 6 reduced elements: And, RS is a trigger equal to 2 reduced elements, and the delay element is equivalent to 1 reduced element I. 123 The number of pulses at the input of the converter

A number-pulse quadratic converter containing two counters, a key, a group of delay elements, a group of emunds I, and an element I, the converter clock input pulses connected to the key information input, the output of which is connected to the input of the first group delay element, output (- i, i 1,2. ... group delay element (where 1 is the number of bits of the first counter) is connected to the input of the (i 1) th group delay element and the first input of the 1st element I of the group, the second input of which is connected to output - first razrada first counter The output of the .t element of the AND group is connected to the counting input i-ro of the second one, characterized in that, with the device simplification circuit, it contains two ibix flip-flops in series with the output of the key being connected to the counting input of the first bit of which is connected through the delay element with the counting input of the first counter, the input clock of the pulse of the amp & form is connected to the input of the first trigger, the output of which is connected to the first input of the AND element and the output of the first bit of the result of the converter, the outputs of the second and third pa rad of which are respectively connected to the zero potential bus converter and the output of the AND, the second input of which is connected to the output of the second flip-flop and the control input .key, the outputs of the transducer, since the fourth ,, are the outputs of the second counter.

Sources of information taken into account in the examination

1. Melnikov, A.A., et al. Processing Frequency and Temporal Pulse Signals, Moscow, Energie, 1976, p. 112-11

2, USSR Author's Certificate No. 315295, cl. H 03 K 23/02, 1970 (prototype). 456789 10

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Claims (1)

Claim A number-pulse quadratic converter containing two counters, a key, · a group of delay elements, a group of elements And and an element And, moreover, the input of clock pulses of the converter 20 is connected to the information input of the key, the output of which is connected to the input of the first delay element of the group, output ( <- rd, ΐ = 1,2 ... the group delay element (where ΐ is the number of times 25 of the first counter) is connected to the input of the (i + 1) th element of the group delay and the first input of the Ίth element of the group AND whose second input is connected to the output of the 1st discharge of the first readout. · (- of the ^; element of the And group is connected to the counting input of the i-ro of the second category, characterized in that, in order to simplify the device, it contains two triggers connected in series, and the output of the key is connected with the counting input of the first discharge and the second counter, the output of the second discharge of which is connected through the delay element to the counting input of the first counter, the input of the clock pulses of the converter is connected to the input of the first trigger, the output of which is connected to the first input of the element And and the output of the first discharge at the converter, the outputs of the second and third bits of which are connected respectively to the bus of the zero potential of the converter and the output of the element And, the second input of which is connected to the output of the second trigger and the control input of the key, the outputs of the converter, starting from the fourth, are the outputs of the second counter,