SU1149159A1 - Multi-channel device for location of acoustic emission sources - Google Patents

Abstract

MULTI-CHANNEL DEVICE FOR LOCATION OF SOURCES OF ACOUSTIC EMISSION, containing n channels, each of which contains a series-connected electroacoustic transducer and amplifier-shaper, three triggers, the first circuit of which is OR, the first input of which is connected to the output of the first trigger, and the first prohibition circuit, the inverse input of which is connected with the output of the first OR circuit, and the output with the first inputs of the first and second flip-flops, connected in series the first combination circuit, whose inputs are connected to the outputs Each channel's inhibit circuit, the first delay circuit and the first pulse counter, and a serially connected electronic computing unit and a recorder, are characterized in that, in order to increase the accuracy of the coordinates, it is provided in each channel of clock pulses, the transfer output of which is connected to the first input the third trigger, the channel number register, the multi-bit gate, the information input of which is connected to the outputs of the clock counter, the third trigger and the channel number register, pho the world of synchronized single pulses, the first input of which is connected to the output of the amplifier-maker, and the output to the direct input of the first inhibit circuit, the register whose recording input is connected to the output of the first inhibit circuit, the comparison circuit of the first input of which is connected to the register, the second inhibit circuit whose inverse input is connected to you (L of the first trigger, and the output to the first input of the clock counter, the second OR circuit, the output of which is connected to the second inputs of the clock counter and the third trigger, the first circuit AND, the output of which is connected to the first input of the second SHS circuit, the third prohibition circuit, the inverse input of which is connected to the output of the second trigger, and the output to the second inputs of the first trigger and the second SHS circuit, the second and my, output which is connected to the second input of the second trigger, the third OR circuit, the third AND circuit, the output of which is connected to the first input of the second circuit Nickname of the control input of the multi-bit valve, the fourth And circuit, the first input of which is connected to the output of the second trigger, the second to the output of the comparison circuit, and the output to the first inputs of the first and third circuits AND and the third circuit OR, and an inverter whose output is connected

Description

to the second input of the third circuit AND, common to the whole device by a clock pulse generator, the output of which is connected to the second inputs of synchronized single pulse drivers and to the direct inputs of the second inhibit circuits of each channel connected in series by the second combining circuit, whose inputs are connected to the outputs of the fourth AND circuits each channel, a second delay circuit and a second pulse counter, a multi-bit combining circuit whose inputs are connected to the outputs of the multi-discharge gates of each channel, and An additional comparison circuit and an additional AND circuit, the first input of which is connected to the output of the additional comparison circuit, and the output to the second inputs of the first IZH circuits of each channel made with two inputs, the output of the first delay circuit is connected to the forward inputs of the third prohibition schemes of each channel code code first

the pulse counter is connected to the first input of the additional comparison circuit and to the information inputs of the registers of each channel, the output of the second pulse counter is connected to the second input of the additional comparison circuit and to the second inputs of the comparison circuit of each channel, the output of the second combination circuit is connected to the iTofoMy input of the additional And circuit and the first input of the electronic computing unit, the second input of which is connected to the output of the multidisk combining circuit, and the second output to the second inputs of the second circuits AND of each channel, input d the inverter and the second inputs of the third OR circuit and the first AND circuit of each channel, except the first one, are connected to the output of the third OR circuit of the channel with the MDM number one less than the channel number, and in the first channel these inputs are intended to be connected to the logical source zero

The invention relates to non-destructive testing and can be used to determine coordinating defects in products. A multichannel device for locating acoustic emission sources is known, which contains registers, OR circuits, triggers, clock generator, AND circuit, clock counter, electronic-calculator unit, recorder, and a channel consisting of a converter and an amplifier-former. In addition, the device also contains the encoder l. The disadvantage of such a device is low speed, since its operation provides for a period of locking the input circuits at readout time into the electronic computing unit of information about the future acoustic emission, comparable in magnitude to the maximum difference in arrival times for a given location. makers. In addition, the device may not fix (or fix incorrectly) the transducer number in the case of simultaneous arrival of the wave front to several transducers, the probability of which can reach a significant value with a large number of transducers and high acoustic emission activity. The closest in technical essence and the achieved effect to the invention is a multichannel device for locating acoustic emission sources, containing P channels, each of which contains a series-connected electro-acoustic transducer and a booster amplifier, three triggers, the first OR circuit, the first input of which is connected to the output the first trigger, and the first prohibition scheme, the inverse input of which is connected to the output of the first OR circuit, and the output to the first inputs of the first and second triggers, followed by preferably connected first merge circuit, inputs

which is connected to the outputs of the first inhibit circuits of each channel, the first delay circuit and the first pulse counter, and a serially connected electronic computing unit and a recorder. In addition, the device contains two time-interval meters, an encoder, a switch, and a concordance unit 2j

A disadvantage of the known device is the low accuracy of determining the coordinates, since only information from the first three triggering channels is taken into account, which excludes the possibility of spatial-temporal filtering of signals. The first three transducers can belong to different groups (antennas) and operate from different sources, thus, fixed at this information will be insufficient to calculate the coordinates; when a wave front simultaneously arrives at two or more transducers, their numbers can be fixed incorrectly due to the operation of several identical triggers in different channels. In addition, the device locks all n channels for the duration of reading information into the electronic computing unit, which is another drawback in monitoring products with a high level of acoustic emission activity.

The purpose of the invention is to increase the reliability of determining the coordinates.

The goal is achieved by the fact that a multichannel device for locating acoustic emission sources containing n channels, each of which contains a series-connected electroacoustic transducer and a driver amplifier, three triggers, the first OR circuit, the first input of which is connected to the output of the first trigger, and the first prohibition circuit , the inverse input of which is connected to the output of the first OR circuit, and the output to the first inputs of the first and second triggers, serially connected to the first combining circuit, in which rows are connected to the outputs of the first circuits prohibition each channel, a first delay circuit and the first pulse counter and sequentially connected cathode-computing unit and the recorder is provided in each channel counter clock pulses carry output of which is connected to

the first input of the third trigger, the channel number register, a multi-bit valve, the information input of which is connected to the clock counter outputs, the third trigger and the channel number register, the synchronized single pulse driver, the first input of which is connected to the output of the formformer amplifier, and the output to the output the first input of the first prohibition circuit, the register whose recording input is connected to the output of the first prohibition scheme, the comparison circuit, the first input of which is connected to the register output, the second prohibition scheme, inv The pc input of which is connected to the output of the first trigger, and the output to the first input of the clock counter, the second OR circuit, the output of which is connected to the second inputs of the clock counter and the third trigger, the first And circuit, the output of which is connected to the first input of the second OR circuit, the third prohibition scheme, the inverse input of which is connected to the output of the second trigger, and the output to the second inputs of the first trigger and the second OR circuit, the second AND circuit, the output of which is connected to the second input of the second trigger, the third OR circuit, the third And the output of which is connected to the first input of the second AND circuit and to the equalizing input of the multi-bit valve, the fourth AND circuit, the first input of which is connected to the output of the second trigger, the second to the input of the comparison circuit, and the output to the first inputs of the first and the third AND circuit and the third OR circuit, and an inverter, the output of which is connected to the second input of the third AND circuit, common to the entire device by a clock pulse generator, the output of which is connected to the second inputs of the synchronized single pulse drivers and to the forward inputs v each channel banned circuits connected in series by a second combining circuit, the inputs of which are connected to the outputs of the fourth circuits AND of each channel, a second delay circuit and a second pulse counter, a multi-bit combining circuit, the inputs of which are connected to the outputs of the multi-discharge gates of each channel, and an additional circuit comparison and additional circuit AND, the first input of which is connected to the output of the additional comparison circuit, and the output - to the second inputs of the first OR circuit of each channel, filled with two inputs and, the output of the first delay circuit under the keys to the direct inputs of the third inhibit circuit of each channel, the output of the first pulse counter is connected to the first input of the additional comparison circuit and to the information inputs of the registers of each channel, the output of the second pulse counter is connected to the second input of the additional comparison circuit and the second inputs of the comparison circuits of each channel, the output of the second combination circuit is connected to the second input of the additional AND circuit and to the first input of the electronic computing unit, the second input of which is connected n to the output of the multi-bit combining circuit, and the second output to the second inputs of the second AND circuit of each channel, the input of the inverter and the second inputs of the third OR circuit and the first AND circuit of each channel, except the first, are connected to the output of the third ELI channel with the number one smaller than the number of this channel, and in the first channel the indicated inputs are intended to be connected to the logical zero source. Figure 1 shows a functional diagram of a multichannel device for locating acoustic emission sources; Fig. 2 shows temporary diagrams, in which a device operation is shown. The device contains And channels, each of which consists of a series-connected electroacoustic transducer 1, an amplifier-former 2 and a former 3 synchronized single pulses, the first prohibition circuit 4, the input of which is connected to the output of a single-trigger 5, second trigger trigger 6, the first inputs of which are connected to the code of the first prohibition circuit 4, the first IZH circuit 7, the first input of which is connected to the output of the first trigger 5, and the output to the inverse input of the first Schemes 4 of the prohibition, connected in series to the second scheme B of the prohibition, the inverse input of which is connected to the output of the first trig 55

Hera 5, and 9 counters clock pulse, the third trigger 10, the first input of which is connected to the output ne1

the input to the output of the second combining circuit 27, and the output to the second inputs of the first circuits OR 7 of each channel. 59 renos counter 9 clock pulses, channel number register 11, multi-discharge valve 12, whose information input is connected to the outputs of the clock pulse counter 9, the third trigger 10 and the channel number register 11, the second OR circuit 13, the code of which is connected to the second inputs of the counter 9 clock pulses and the third trigger 10, serially connected register 14, the recording input of which is connected to the output of the first prohibition circuit 4, and the comparison circuit 15, the first circuit 16, the output of which is connected to the first input of the second circuit 13, third with prohibition scheme 17, the inverse input of which is connected to the output of the second trigger 6, and the output to the second inputs of the second circuit. we have ShZh 13 and the first trigger 5, the second circuit AND 18, the output of which is connected to the second input of the second trigger 6, the third circuit OR 19, the third circuit AND 20, the output of which is connected to the first input of the second circuit And 18 and to the control input of the multidisc valve 12, the fourth circuit AND 21, the first input of which is connected to the output of the second trigger 6, the second input to the output of the comparison circuit 15, and the output to the first inputs of the first circuit and 16, the third circuit AND 20 and the third circuit OR 19 and the inverter 22, the output of which is connected to the second input of the third circuit And 20, common to the entire device A generator of 23 pulses, the output of which is connected to the direct inputs of the second inhibitor circuits 8 and the second inputs of the formers 3 synchronized single pulses of each channel, are connected in series to the first combining circuit 24, the inputs of which are connected to the outputs of the banning circuits 4 of each channel, first circuit 25 delays and the first pulse counter 26, connected in series to the second combining circuit 27, the inputs of which are connected to the outputs of the fourth circuit 21 of each channel, the second delay circuit 28 and the second counter 2 9 pulses, additional comparison circuit 30, additional circuit I 31, the first input of which is connected to the output of additional comparison circuit 30, the second

a multi-bit combining circuit 32, the inputs of which are connected to the outputs of the multi-bit valves 12 of each channel, and a series-connected electronic computing unit 33, the first input of which is connected to the output of the second combining circuit 27 and the second input to the output of the multiplexing combining circuit 32, and the recorder 34. The output of the first delay circuit 25 is connected to the direct inputs of the third circuit 17 of the prohibition of each channel. The second output of the electronic computing unit 33 is connected to the second inputs of the second circuits And 18 of each channel. The output of the first pulse counter 26 is connected to the first input of the additional comparison circuit 30 and to the information inputs of the registers 14 of each channel, and the output of the second pulse counter 29 to the second input of the additional comparison circuit 30 and to the second inputs of the comparison circuit 15 of each channel. The input of the inverter 22 and the second inputs of the third circuit OR 19 and the first circuit AND 16 of each channel, except the first, are connected to the output of the third circuit OR 19 with the number one less than the number of this channel, and in the first channel these inputs are intended to be connected to source 35 logical zero.

The device works as follows.

In the initial state (in the absence of acoustic emission signals for some time), the first and second counters 26 and 29 of the pulses are in the same, for example, jp-OM state, the first and second triggers 5 and 6 of each channel are reset, the counters 9 clock the pulses of each channel synchronously measure the time interval from the last acoustic emission signal received by the device. The third triggers 10 of each channel, registering the overflow of the counters of 9 clocks, are in the state, respectively

but, one or zero, depending on whether or not the value of the specified interval exceeds the value

where f.T (j clock frequency

impulses output by generator 23;

S is the number of bits in the counter 9 clock pulses. The resulting voltage waves, as a result of the development of defects and deformations of the structure, are converted by the converter 1 nearest to the source, for example, a channel into an electrical signal, and further amplified and normalized by the driver former 2. Its output signal is shown in plot 36 (Fig. 2). The pulse 37 on the leading edge of this signal synchronized with the clock pulses 38, from the output of the forker 3 synchronized single pulses passes through the open first prohibition scheme 4, sets on its trailing edge the first and second triggers 5 and 6 into one (diagrams 39 and 40, respectively) and rewrites into register 14 the status code j of the first counter of 26 pulses. In this case, the second prohibition scheme 8 blocks the further arrival of pulses 41 to the input of the counter 9 clock pulses, the first prohibition scheme 4 blocks the passage of other pulses 37 in this channel, if they occur. The comparison circuit 15, due to the coincidence of the register codes 14 and the second pulse counter 29, generates a potential passing through the fourth circuit 21 and the second combination circuit 27 to the first input of the electronic computing unit 33 as an information input request signal 42. The same potential through the third circuit And 20 opens the multi-bit valve 12. Thus, the code of the channel number recorded on the counter 9 clock imI

pulses the time interval code together with the overflow discharge from the third trigger 10 is received through the multi-bit valve 12 and the multi-bit combining circuit 32 to the second input of the electronic computing unit 33 for input, for example, via a direct memory access channel to the pulse from the output the first prohibition scheme 4, through the first unification scheme 24 and the first scheme 25 per circuit, ne, converts the first pulse counter 26 to the next (j + Oe state (plot 43) and then, through the open third prohibition schemes 17, all channels except this one sets in ul Fernie area of its RAM. In addition.

counters 9 clock pulses and third trigger 10 of all channels except this one, after which a synchronous count of the new time interval begins in them. After the end of the session, the electronic computing unit 33 forms the input output signal 44 at the second output, which, through the second circuit 18, resets the second flip-flop 6 of this channel (plot 40). The third blocking circuit 17 of this channel is opened, the multi-bit valve 12 is closed, the input request signal 42 is removed, and on its trailing edge, it is delayed; In the second delay circuit 28, the unit is added to the second pulse counter 29. Next, a voltage wave appears in the channel, whose converter 1 is located at a greater distance from the source, the leading edge of the amplified and normalized signal 45, synchronized with the clock pulses, passes through the same elements in this channel (plots 37, 39, 40 and 41 correspond to diagrams 46, 47, 48, 49), fixes 9 clocks of this channel on the counter, the value of the time interval, which was counted from the moment of arrival of the wave to the converter 1 of the previous one, in this case channel, initiates the input of the code of this interval, also the code of the number of this channel in the electronic computing unit 33, then through the first combining circuit 24, the first delay circuit 25 and the third prohibition circuit 17 resets the counters 9 clock pulses and the third flip-flops to other channels, including the i, -th channel, thus starting the next time interval into them, as well as the first trigger of the 5 1 | th channel (plot 39), allowing, thus, the new acoustic emission signal in it, and adding one, to the first counter 26 pulses . At the end of the input session, as in the previous case, the second flip-flop 6 of this channel is reset, which prepares to flush the first flip-flop 5 of this channel with a subsequent acoustic signal received on any other channel, and also one is added to the second counter 29 pulses . When new signals arrive

acoustic emission process is repeated.

In the event that another one or several channels are triggered during the input of the next information in the electronic access control unit 33, sequential numbers generated by the first pulse counter 26 will be assigned to all of them, since it counts modulo 2, where m is the width of the first and second counters 26 and 29 pulses, the highest number is automatically followed by a zero number. After the input session started earlier and the unit is added to the second pulse counter 29, the input of the channel that triggered before the others begins, since it is in its register 14 that the code coincides in the comparison circuit 15 with the current state code of the second counter 29 pulses and t .d., until all the information accumulated in the channels has been entered. The device provides protection against failures in determining the order of reading information when the number of channels or groups of simultaneously triggered channels requiring a session with electronic unit 33 has reached Z. In this case, all possible j numbers are used, and the subsequent numbering of the channels becomes impossible until information from at least one channel (or a group of channels, in the event of their simultaneous operation) is read. A sign of such a critical situation is the coincidence of the codes in the first and second counters 26 and -29 pulses, as well as, unlike in the quiescent state, the presence of an input request signal. At the same time, at the output of the additional scheme I 31, a signal is generated, which, through the first OR 7 schemes of each channel, closes the first prohibition schemes 4, thereby blocking the passage of acoustic emission signals.

At the same time, with an accuracy of one clock period following the triggering of one or several channels, the same number j is simultaneously written to their registers 14. In this case, the issue of prioritizing channels when reading is decided depending on the order of the spatial arrangement of these channels in the device so that the highest priority is received by the channel with the lowest number i. For this, the request signal from the channel with the smallest number i, the passage through the chain of third circuits OR 19, blocks information from other channels using inverters 22 and third AND 20 circuits. At the same time, in channels with the same current number j, but more number i, at the outputs of the first circuits AND 16, the signal that passes through the second circuits OR 13 is violated; it resets the counters of 9 clock pulses and the third triggers 10 of these channels, thereby setting zero time intervals between simultaneously triggered channels, Srau after entering the information From the channel with the smallest number i, the input starts from the next spatial order of the channel, etc., and the input request signal is not interrupted. After entering information from the last of the group of simultaneously triggered channels, the rising edge of the millet signal 912 is formed, one is added to the second pulse counter 29, and further information is entered in order of the j numbers that determine the order in which the channels are triggered. The electronic computing unit 33, as information is accumulated, for example, in the buffer area of its RAM, performs its space-time filtering and determines the coordinates of the acoustic emission sources. The results of the calculations are output to the recorder 34. The invention allows for the counting of time intervals on almost all channels, having received this acoustic emission signal, which greatly expands the possibilities of space-time filtering and allows to increase the accuracy of determining the coordinates. In addition, it provides the ability to measure when high activity of acoustic emission, eliminates the limitations associated with simultaneous operation of the channels.

Claims (1)

MULTI-CHANNEL DEVICE FOR LOCATION OF SOURCES OF ACOUSTIC EMISSIONS, containing η channels, each of which contains a series-connected electro-acoustic transducer and amplifier-driver, three triggers, the first OR circuit, the first input of which is connected to the output of the first trigger, and the first inhibit circuit, whose inverse input is connected with the output of the first OR circuit, and the output with the first inputs of the first and second triggers, connected in series with the first combining circuit, the inputs of which are connected to the outputs of the first m prohibition each channel, a first delay circuit and the first pulse counter and sequentially connected cathode-computing unit and the recorder, wherein; that, in order to increase the reliability of determining the coordinates, it is equipped with a clock counter in each channel, the transfer output of which is connected to the first input of the third trigger, a channel number register, a multi-bit valve, the information input of which is connected to the outputs of the clock pulse counter, third trigger and register the channel number, by the generator of synchronized single pulses, the first input of which is connected to the output of the amplifier-driver, and the output to the direct input of the first inhibit circuit, by register whose recording input is connected to the output of the first inhibit circuit, a comparison circuit whose first input is connected to the register output, a second inhibit circuit whose inverse input is connected to the output of the first trigger, and the output to the first input of the clock counter, the second OR circuit, output which is connected to the second inputs of the clock counter and the third trigger, the first AND circuit, the output of which is connected to the first input of the second OR circuit, the third inhibit circuit, whose inverse input is connected to the output of the second trigger, and the output - to the second inputs of the first trigger and the second OR circuit, the second AND circuit, the output of which is connected to the second input of the second trigger, the third OR circuit, the third AND circuit, the output of which is connected to the first input of the second Inc circuit, the control input of the multi-bit valve, the fourth AND circuit, whose first input is connected to the output of the second trigger, the second to the output of the comparison circuit, and the output to the first inputs of the first and third AND circuits and the third OR circuit, and an inverter whose output is connected> * 149159 to the second input of the third AND circuit, common to the entire device by a clock generator, the output of which is connected to the second inputs of the formers of synchronized single pulses and to the direct inputs of the second blocking circuits of each channel, serially connected by the second combining circuit, the inputs of which are connected to the outputs of the fourth circuits And each channel, a second delay circuit and a second pulse counter, a multi-bit combining circuit, the inputs of which are connected to the outputs of the multi-bit gates of each channel, and additional An additional comparison circuit and an additional AND circuit, the first input of which is connected to the output of the additional comparison circuit, and the output to the second inputs of the first OR circuits of each channel made with two inputs, the output of the first delay circuit is connected to the direct inputs of the third inhibit circuits of each channel , the output of the first pulse counter is connected to the first input of the additional comparison circuit and to the information inputs of the registers of each channel, the output of the second 'pulse counter is connected to the second input of the additional comparison circuit to the second inputs of the comparison circuits of each channel, the output of the second combining circuit is connected to the second input of the additional circuit And to the first input of the electronic computing unit, the second input of which is connected to the output of the multi-bit combining circuit, and the second output to the second inputs of the second circuits And of each channel , the inverter input and the second inputs of the third OR circuit and the first AND circuit of each channel, except the first, are connected to the output of the third OR circuit of the channel with a number one less than the number of this channel, and in the first channel the indicated inputs dy are designed to connect to a source of logic zero.