SU1667121A1 - Data input device - Google Patents

Abstract

The invention relates to automation and computing, in particular to information reading devices, followed by input into a computer. The purpose of the invention — improving the accuracy of the device — is achieved by introducing three keys, six flip-flops, three comparators, eleven AND elements, two inverters, three counters, two shift registers, a delay element, a pulse generator, an adder, four registers, and an OR element block, which allows fix the size and the beginning of the location of the array of information. 4 il.

Description

 The invention relates to automation and computing, in particular to information reading devices, followed by input into a computer.

The purpose of the invention is to improve the accuracy of the device.

FIG. 1 shows a block diagram of the proposed device; Figs, 2, 3, and 4 show signal plots at various points in the device.

The device (Fig. 1) contains a reading unit 1, an amplifier unit 2, the first 3, second 4 and third 5 keys, first 6 and second 7 elements OR, first 8, second 9, third 10, fourth 11, fifth 12, sixth 13 and seventh 14 triggers, first 15, second 16 and third 17 comparators, first 18, second 19, third 20, fourth 21, fifth 22, sixth 23, seventh 24, eighth 25, ninth 26, tenth 27 and eleventh 28 elements And, the first 29 and second 30 inverters, the first 31, the second 32 and the third 33 counters, the first 34 and second 35 shift registers, the adder 36. delay element 37, the generator 38 pulses, the first 39 , second 40, third 41

and the fourth 42 registers and a block of 43 elements OR.

The device works as follows.

The reading unit 1 reproduces the information recorded on a magnetic tape in the form of a binary multi-bit word accompanied by clock pulses (Fig. 26). FIG. 2a shows a plot of a single input signal, represented in analog form. The information on the carrier is represented as frames separated from one another by a personnel impulse. These pulses are present at the second clock output of read unit 1 (Fig. 2c). Each frame consists of a series of informational, service and marker multi-bit binary words. The number of bits is eight, i.e. information is read by individual bytes. The information bytes contain the code of a certain number characterizing the analog signal at the time of measurement. Possible boundaries for the measurement of codes in the case of using an eight-digit binary number lie in the range from 0 to 255, and information

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bytes contain only numbers ranging from N 1 to N 2, with 0 N1 N2 2П -1, where n is the number of bits. Service and marker information also lie within the specified limits and occupy the penultimate and last word in the frame. In the operation of this device, their contents are not used.

Frame pulses (Fig. 2c) are received between the service and marker words. To completely zero the marker word, the second 9 trigger is used, which is cocked by the leading edge of the frame pulse from the second clock output of the amplifier block 2 (Fig. 2c). The latter serves only to bring the readout unit 1 reading to a form convenient for the operation of further electronic circuits. The flip-flop 9 is reset by the falling edge of a pulse from the first clock output of the amplifier unit 2 (Fig. 26). The negative pulses thus generated (Fig. 2d) at the inverse output of the second 9 flip-flop close the first 3 key during the passage of the marker signal. Codes of all other signals are passed to the output of the first 3 key. Codes coming from the output of the first 3 key are compared in the first 15 comparator to equality to code N 2, where N 2 is the maximum possible recorded number in information words. When registering information, the appearance of this code informs about the overflow of information in the corresponding word of the frame. A sign of the boundaries of the zones of recorded information is the recording of overflow codes on all channels of the recorded frame. Therefore, in order to highlight the indicated boundaries, it is necessary to detect a section in the incoming information, where the information signals are constantly equal to the overflow code, i.e. N 2. In these zones, overflow records may include areas with the short-term appearance of codes of other digits other than N 2.

In the first 39 register, a code of a number equal to N is preliminarily recorded. At the output of the first 16 comparator, there is a unit level at the moments of equality of the incoming numbers N 2. At the first 18 element I, they are gated. The pulses at the output of the first 18 element And are presented in FIG. 2d

To separate the frames from each other, the first 6 element OR is used. Since / ak only the marker word is completely zero, then at the moment of its passage at the output of the first 6 element OR there will be zero information, 8 the rest of the time is single. The zero level from the output of the first 6 element OR, inverted in the first 29 inverter, is gated in the third 20 element AND by the synchronizing pulses (Fig. 26). At the output of the third element 20, there are pulses at the moment of the marker information (Fig. 2e). In fact, these are pulses that separate neighboring frames from one another. The zeroing of the first 29 counter occurs on the falling edge of these pulses. So in this counter for

0 of one frame is summed by the number of bytes equal to N 2 by applying pulses from the output of the first 18 element AND (Fig. 2e).

Not all informational words in a frame in zone separation mode can be equal.

5 N 2. Some of them may have other meanings due to random failures. If the total number of information words in a frame is K, then if m words in a frame are N 2, where m K, we can assume that this frame

0 serves as an overflow frame. The number m is pre-recorded in the second 45 register. If the code at the output of the first 31 counter equals or exceeds the number of t, then at the output of the second 16 digital

5, a single signal appears (Fig. 2g). The plots of FIG. Figures 2-4 show signals for cases m 6 and 5. This positive level (Fig. 2g) is gated with a pulse from the output of the second 19 element AND to

0, p 22 element I. The pulses from the output of the latter (Fig. 2h) are cocked by the leading edge of the Fifth 12 trigger (Fig. 2i), and it is reset by a pulse from the output of the sixth 23 And element, controlled by the third 10 trigger 5 (Fig. 2k).

The signal from the fifth 12 flip-flop (Fig. 2i) serves as an information signal for the first 34 shift register. Sequential reception and shift in it

0 occurs on the leading edge of the synchronizing pulse (Fig. 2e) from the output of the second 19 element I.

Due to random emissions in the measured signal in the middle of the array entered

5 information, all information words in individual frames may be equal to N 2. To eliminate the erroneous recognition of a zone boundary, the number of overflow frames in the last S frames is determined. If this number is greater than or equal to S 1, then it is considered that this is not a random overflow frame, but a zone boundary.

The definition of the number S is as follows.

5 If the first bit of the shift register 34 is entered with a single information (Fig. 2i), and from the last one is output zero, then the number of ones in the bits of the register 34 is increased by one. The signal at the output of the adder 36 modulo two will be equal to

zero, and inverting in the second 30 inverter, the positive signal will go to the second inputs of the seventh 24 and eighth 25 elements I. However, the pulse in the output of delay element 37 will pass to the output of only the seventh 24 AND element, since only its first input will allow the signal from the output of the fifth 12 trigger (Fig. 2i). The impulse from the output of the seventh 24th element will go to the summing input of the second 32 counter. The code at its output will be one more. In the initial state, the second 32 counter is reset.

If a zero signal is inputted to register 34 and a single signal is output, a similar impulse will go to the subtractive input of the second 32 counter. If the input and output codes from register 34 are equal, a single signal from the output of the adder 36 modulo two, inverted in the second 30 inverter, turns into a zero level. The latter closes the seventh 24th and eighth 25th elements I. There will be no change in the state of counter 32 in this case.

Thus, the current code at the output of the second 32 counter is equal to the number of units available in the bits of the first 34 shift register, i.e. number S. The third 41 register is preliminarily entered into a code of a number equal to S 1. At the output of the third 17 digital comparator, a unit level is reached (Fig. Zl) if the code of the number S from the output of the counter 32 exceeds the code of the number S 1 from the register 41 At the control input of the fourth 11 flip-flop a unit level. The latter is made in the form of a D-flip-flop, so this unit level is at its output (Fig. 3M) along the trailing edge of the first synchronizing pulse (Fig. 3e). The leading edge of the signal from the output of the fourth 11 flip-flop (fig. 3m) will set the first 8 flip-flop (fig. 3n, inverse output), sixth 13 flip-flop (fig. Zl), seventh 14 flip-flop (fig. 3p) to the single state. In this case, the second 5 key will be opened and the code recorded in the fourth 42 register will be received at the output of the device through the block of 43 elements OR. The synchronizing pulse to the other output of the device will come from the generator 38 pulses (Fig. 3c and 4c) through the open eleventh 28 element I.

The signal from the output of the trigger 13 will enable the operation of the pulse generator 38 (Fig. 3c), the signals from which pass through the open tenth 27 And element and enter the counting input of the third 33 counter, which switches on the falling edges of the incoming pulses (Fig. 3c). ). The third 33 counter is pre-zeroed by the falling edge of the signal from the inverse output of the seventh 14 flip-flop (Fig. 3p., The signal from the direct output is shown). An overflow pulse at the output of the third 33 counter is formed after a predetermined number of pulses are supplied from the pulse generator 38 (in Fig. 3c - three). This impulse will return to its original state the seventh 14 trigger (fig. 3p), thereby supplying the enabling signal to the second input of the ninth 26th element I. However, the latter will open, i.e. will let pulses from generator 38 (Fig. 3c) pass to its output only if it receives a single signal from the inverse output of the fourth 11 flip-flop (Fig. 4m shows the signal from the direct output). Single signals on the first and second inputs of the tenth 26th element And can appear in any order. This depends on the size of the overflow zone (Fig. 2a, 3a, 4a). pulse frequency from generator 38 (Fig. 3c, 4c) and the volume of the third 33 counter. In the diagrams (Figs. 3 and 4), as an example, a positive signal at the first input appears later than at the second input of element 26 I. The fourth 11 trigger (Fig. 4m) will be reset if its control input is (Fig. 4l) Wits zero level. This will happen when the number of 1 bits in the first 34 shift register S becomes less than the number S 1 recorded in the third 41 memory register. After that, the first impulse from generator 38 (FIG. 4c) passes to the reset input of the sixth-13 flip-flop and sets it to zero with a falling front (FIG. 4p). A zero signal from the output of the trigger 13 (Fig. 4p) will prohibit the operation of the generator 38 and close the eleventh 28th element AND, the third key 5. This level also removes the prohibition from the operation of the second 35 shift register. In this case, in the first of its discharge unit is set. Its output bit is the third. Therefore, upon the occurrence of the second positive edge on the synchronization input of the register 35 (Fig. 4a) at the output of the last positive signal (Fig. 4y). Its leading edge will set the first trigger 8 to the initial state (Fig. 4n).

As a result of the operation of the device, codes from the reading unit will be transmitted to its information output without changing at the beginning of operation via the open second 4 key with the signal from the inverse output of the first 8 flip-flop (Fig. 2n). During the readout of the overflow zone, the output of the device through the open third 5 key and the block 43 of the elements OR will pass the code from the fourth 42 memory register located behind

outside the codes N 1 N 2 and not equal to zero, for example, a code equal to one if. After reading the overflow zone, the code to the output of the device also comes from the reading unit 1. At the output of the second 7 element OR, output clock pulses (Fig. 2m, 3m, 4t) will be formed from the sequentially open elements AND, first the fourth 21 elements AND, then the eleventh 28 and finally the fourth 21 elements I.

Claims (1)

Invention Formula An information input device comprising a reading unit, the first, second and third outputs of which are connected to the first and second control inputs and the information input of the amplifier unit, the first output of which is connected to the information input of the first key, the output of which is connected to the inputs of the first OR element, first the trigger, the inverse output of which is connected to the control input of the second key, the information input of the second key is connected to the output of the first key, characterized in that, in order to increase the accuracy of the device, it holds the third key, the second element OR, the second - the seventh trigger, three comparators, eleven AND elements, two inverters, three counters, two shift registers, a delay element, a pulse generator, an adder, four registers and a block of OR elements whose output is an output device, the output of the second element OR is the second output of the device, the first and second inputs of the block of elements OR are connected to the outputs of the second and third keys, the information input of the third key is connected to the output of the fourth register, the output of the sixth trigger - with the input Reset the second shift register, the control input of the pulse generator, the first input of the fourth And element and the control input of the third key, the second output of the amplifier unit is connected to the Reset input of the second trigger, the first inputs of the first to fourth And elements connected to the outputs of the first comparator , the first element is NOT, the first element is OR and the inverse output of the first trigger, the output of the second element is AND is connected to the input Reset the first counter, the first input of the fifth element AND, the installation input of the third trigger pa, gating inputs of the first and second shift registers, the input of the delay element and the gate input of the fourth trigger, the information input of which is connected to the output of the third comparator, the first input of which is connected to the output the third register, and the second with the output of the second counter, the counting inputs of which are connected to the outputs of the seventh and eighth And elements, the output of the fifth trigger is connected to the information input of the first shift register, the first inputs of the adder and the seventh And element, the output of the first shift register with the second the input of the adder and the first input of the eighth element And, the output of the adder is connected to the input of the second element NOT, the output of which is connected to the second inputs of the seventh and eighth elements And, the third inputs of which are connected to the output of the element beyond holders, setup trigger input connected to the output of the fifth element And, the second input of which is connected to the output of the second comparator, the inputs of which are connected to the outputs of the second register and the first counter, strobe the input of which is connected to the output of the first element And, the output of the third element And is connected to the reset input of the third trigger and the first input of the sixth element And, the second input of which is connected to the output of the third trigger, and the output is with the input Reset of the first trigger, the direct output of the fourth trigger is connected to the setup inputs of the first, sixth and seventh trigger, the inverse output of the fourth trigger is with the first the input of the ninth element And whose output is connected to the input Reset the sixth trigger, the direct output of the seventh trigger is connected to the first input of the tenth element And, and the inverse output to the second input of the ninth element And and the input Reset the third counter, the output of the pulse generator is connected with the third input of the ninth element And, the second inputs of the tenth and eleventh elements And, the output of the latter is connected to the first input of the second element OR, connected to the output of the fourth element And, the third output of the amplifier unit is connected to the nym input of the second flip-flop inverse output of which soedi0 nen to a control input of the first switch, whose output is connected to a first input of the first comparator, a second input coupled to an output of the first register, output of the first OR element connected to the input 5 of the first element NOT, the output of that element I - with the gate input of the third counter, the output of which is connected to the input Reset of the seventh trigger. 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