SU1541586A1 - Timer - Google Patents

Abstract

The device relates to computing technology and can be used in control computing complexes operating in real time. The aim of the invention is to increase speed. This goal is achieved by introducing element 6, element 8, register 8, selectors 11. A distinctive feature of the sensor is that there are no prohibition intervals for outputting information in the digital computer, i.e. increased speed of the exchange of digital computers with a time sensor. There is no need to synchronize the read request signal with the operation of the time sensor, the possibility of reading an erroneous time code is excluded. 2 Il.

Description

Read request

5CM

ate

4i

SD

00 Oh

 Initial burden

Fy9.1

The invention relates to computing and can be used in control computing systems operating in real time.

The purpose of the invention is to increase the speed

Figure 1 presents the functional diagram of the sensor; figure 2 - the timing diagram of his work.

The time sensor contains a generator of 1 pulses, a counter of 2 pulses, a decoder 3, a divider 4 frequencies, a trigger 5, elements 6 and 7, an element NOT 8, a counter 9 time, a register 10, a selector 11, an input 12 of the initial installation, an outputs 13.

The sensor works as follows.

With the inclusion of a time sensor, the initial setting of the counter 2 pulses occurs and the initial value of the time code from the digital computer in the counter 9 is set. The high frequency pulses (Fig. 2a) are fed from the output of the generator 1 to the input of counter 2. The signals from the outputs of counter 2 arrive at the corresponding inputs of the decoder 3, the outputs of which form three sequences of pulses b, c, d, shifted relative to each other by a time interval T, (Fig.26, c, d). The impulses of the sequence b from the first output of the decoder 3 are fed to the input of the divider 4 frequency, which produces the current time samples (fig.2d), synchronized with the pulses b. In addition, the pulses of the sequence b are fed to the input of the unit in the unit, and the pulses of the sequence Mr. to the reset input to the O flip-flop 5, produce its sequential switching (fig.2e).

Element And 6 from the sequence e from the output of the trigger 5 and the sequence d from the output of the divider 4 forms at its output the resulting sequence g (Fig. 2g), and the element And 7 from the sequence e and the sequence in from the second output of the decoder 3 forms the sequence C (Fig .2z), arriving at the counting input of the time counter 9 and calculated by it.

The time code from the time counter is recorded in the register 10 by the trailing edge of the pulses W (by

0 Q 5

five

five

the voltage difference from O to 1) from the element is NOT 8 after the information in counter 9 has changed, according to the impulse h. Pulses with which information is changed in time counter 9 are reliably overlapped by pulses; in the time interval w (logic level 1), information is output to the digital computer from register 10 through selectors 11, and the rest of the time information to digital computers comes through selectors 11 directly from the counter.

The information in the digital computer from the selectors 11 comes in the case of the presence at the input of a request for reading a time sensor of positive potential.

Claims (1)

Invention Formula A time sensor containing a clock pulse generator, a time counter, a pulse counter, a decoder, a frequency divider, the first element I and a trigger, the output of the clock generator connected to the counter input of the counter, the bit outputs of which are connected to the decoder’s first output the information input of the frequency divider and with the input of the installation in 1 trigger, the second output of the decoder is connected to the first input of the first element And, the third output of the decoder is connected to the reset input in About the trigger, the output of the The frequency cell is connected to the second input of the first element AND, the output of which is connected to the counting input of a time counter, the group of information inputs of which is a group of inputs for setting the initial time of the sensor, the enable input for recording the time counter is connected to the input of the initial installation of the pulse counter and is the input of the initial setting sensor, characterized in that, in order to increase the speed of the sensor, the element is NOT entered, the second element is AND, the register and n selectors "(where n is the number of output channels of the sensor), than vyhod4 griggera connected to the first input of the second AND gate, a second input coupled to an output of the frequency divider, the output of the second AND gate connected to the input of NOT circuit and to the first inputs of the first group the control inputs of the selectors, the first information inputs of which are connected respectively to the outputs of the register, the first inputs of the second group of control inputs of the selectors are connected to the output of the element NOT and to the input of the register recording resolution, the information inputs of which are connected to the outputs of the time counter, the second inputs of the first and second the control input groups of the selector are combined and are the sensor readout input, the selector outputs are the sensor outputs. Schi g, Z