SU454551A1 - Pulse sequence subtractor - Google Patents

Description

one

The invention relates to digital-analogue computing and can be used to obtain an algebraic difference of two pulse frequency.

A device for subtracting pulse sequences is known, which contains two reset valves connected to two identical channels for converting pulse sequences containing lock valves, delay nodes, memory triggers and enable gates.

The purpose of the invention is to simplify the device and ensure operation with an asynchronous pulse train.

The essence of the invention is that in each of the channels the first input of the lock valve is connected to the corresponding input of the subtractor and the first input of the resolution valve, the second input of the lock valve is connected to the second input of the resolution valve and the first input of the delay node, as well as to the output of the first reset valve ; the second input of the delay unit is connected to the output of the blocking valve and to the corresponding input of the first reset valve; the first output of the delay unit is connected to the "single input of the memory trigger, the second output to the corresponding input of the second reset valve; "Zero memory trigger input is connected to the output of the second valve

reset, and the "single output of the memory trigger is connected to the third input of the permit valve and to the corresponding input of the first reset valve.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagrams.

The circuit for the subtraction of pulse sequences contains; and the relief valves 1 and 2; interlock valves 3 and 4, nodes

delays 5 and 6, memory triggers 7 and 8, resolution gates 9 and 10, information channels 1 and 12; input channel 13 And; input 14 of channel 12; output 15 of channel 12; output 16 of channel II; ti-fis are the trigger points of the device elements.

The operation of the device proceeds as follows.

In the initial state (time ti, see Fig. 2), at the inputs of the device there are low potentials "O, corresponding to the absence of input pulses, at the outputs of the device there are high thermals" 1 corresponding to the absence of output pulses; the device triggers are in the “zero position” (the zero position is assumed to be the absence of potentials on the “single outputs of the flip-flops”), the locking valves 3 and 4 are open by the presence of an enable signal “1 coming from the output of the reset valve 1, and

Resolution gates 9 and 10 are closed by the presence of prohibitive signals "O at the outputs of memory triggers 7 and 8.

The operation of the device is carried out in cycles. Each cycle under the action of input pulses translates both channels into the state of resolution of the passage to the device outputs of the input frequency pulses and resets the device into the initial state. The repetition frequency of the cycles is equal to the pulse frequency of the smaller of the input pulse sequences. During one cycle per: device outputs, a ne passes through one pulse of each of the input sequences, and since in one cycle only one pulse of lower frequency arrives at the device’s input, there will be no pulses at the output of that channel to which the lower frequency arrives. On the output of the same channel that receives the highest frequency, there will be pulses, the frequency of which is equal to the frequency difference of the input pulse sequences.

At the beginning and end of the cycle, the described initial state of the device is taken. Suppose that from the beginning of the first cycle (time ti) and to its end (time 4), a single pulse arrived: at input 13, the pulse arrived at time t2- / 3, at input 14 - at time 4- s. , the input pulse will freely pass through it, changing its value to inverse, and, acting on the trigger of the delay node 5, will transfer it to the state "1. In this case, the potential at the first output of the delay node 5 will change from high "1 to low" O only after the end of the input pulse. This actually achieves the delay effect: the signal for switching the trigger of memory 7 will occur only after the end of the input pulse. After the input pulse expires, the "single input trigger of memory 7 from the first output of the delay node 5 will receive a signal" O, which will set the trigger to position "1. Since at this time the output of the relief valve 1 is also at a high potential, the resolution valve 9 opens, thereby allowing passage to the output 16 of the device for subtracting 13 pulses input to the input. The second channel works similarly to the first. Therefore, in the period between time stamps 4 and / 5, channel 12, under the action of a pulse arriving at its input, will set to a position similar to the position of channel 11 during the period At the moment the input pulse (s) terminates at the output of memory trigger 8 potential “1. Since the outputs of the locking valves 3 and 4 and the memory trigger 7 at this time also have high potentials, the reset valve 1 is set to the "O" position. From the output of the reset valve 1, the signal "O" is applied to the first inputs of the delay nodes 5 and 6 and returns the triggers included in them to the initial state. After this happens, on the second

the outputs of the nodes of the delay in TC "units. These "units will cause the appearance of a signal" O at the output of the reset valve 2, which in turn will return to the initial state

memory triggers 7 and 8, and hence the whole device. The process of resetting the device to its original state is almost instantaneous. The return time depends only on the duration of transients on the elements entering the device. So, in the time elapsed before t, the channels of the device under the action of the input pulses are set to allow the passage to the outputs of the device that subtract the input pulses and then reset to their original state.

Now it is necessary to consider the next cycle (4-Y The first pulse of a higher frequency (tj-ts),

as well as in the previous case, opens the resolution valve 9 for the passage of subsequent pulses, but does not pass by itself. The second pulse of this frequency (tto- / 13) passes freely, since it came before the lower frequency pulse () ended, as in the previous case, sets memory trigger 8 to position "1. However, in contrast, the previous case does not reset, since the device provides for blocking the reset for the time it passes through the pulse device. A blockage is introduced to prevent the output pulses from being truncated by lower frequency pulses. It is carried out by applying to the inputs the reset valve 1 from the outputs of the locking valves 3 and 4 inverse input signals. Due to the blocking, the transition of the device to the initial state in the case of coincidence of the pulses of the input frequencies occurs only

after the last of the matched pulses has finished, in this case the pulse. So, during the second cycle, two pulses arrived at the device input 13, and one pulse at the input 14. Respectively,

one pulse for vils at the output 16 of the device.

The diagram shows several more subtraction cycles. As can be seen from the diagram, the operation of the device is not disturbed when the input pulses of equal frequencies coincide. At the input 13 of the device received ten pulses, at the input 14 - seven pulses. Three impulses passed to exit 16. At the exit 15, there were no pulses. If the frequency of arrival of pulses at input 14 would exceed the frequency of arrival of pulses at input 13, the output information would go through output 15 of the device.

Subject invention

A device for subtracting pulse sequences containing two relief valves connected to two identical conversion sequences of pulse sequences including interlock valves, delay nodes, memory triggers and resolution gates, characterized in that, in order to simplify and enable operation with non-synchronous sequences pulses, in each of the channels the first input of the blocking valve is connected to the corresponding input of the subtraction device and, first the input of the resolution valve, the second input One lock valve is connected to the second input of the resolution valve and the first input of the delay unit, as well as to the output of the first

relief valve; the second input of the delay unit is connected to the output of the blocking valve and to the corresponding input of the first reset valve; The first output of the delay node is connected to the “single input of the memory trigger, the second output to the corresponding input of the second reset valve,“ the zero input of the memory trigger is connected to the output of the second reset valve, and “the single output of the memory trigger is connected to the third input of the resolution valve and with the corresponding input of the first relief valve.

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