SU894710A1 - Priority device - Google Patents

Description

(54) DEVICE OF PRIORITY The invention relates to computing, in particular, to devices for priority service of requests. A variable priority device is known comprising a priority register, a counter, a control unit, a cyclic shift register, an analysis unit of a counter for zero, an analysis unit for zero, a high-order unit of cyclic shift register 1. The lack of the device is low speed, due to the successive nature of the analysis of priorities. The closest to the present invention is a device containing a register of requisitions, the outputs of which are connected to the information inputs of the device, priority registers whose outputs are connected to the code input buses of the device, pulse generator, AND, OR, counters and control trigger 2. A disadvantage of the known devices is the complexity of its technical implementation due to high hardware costs, which in turn leads to a decrease in the reliability of the device. The purpose of the invention is to reduce the equipment and increase the reliability of the device. The goal is achieved by the fact that a priority device, containing the request register, group, from n priority registers, where n is the number of the request, a group of n elements AND, two OR elements, pulse generator, AND element, trigger and counter, the group of information inputs of the register is a group of information inputs of the device, the group of information inputs, priority registers are groups of code inputs of the device, each i-th (, ..., n) bit output of the group of discharge outputs of the register of the folder is connected to first entrance The 1st element AND group, the input and the response input of the device are connected, respectively, to the first and second inputs of the first OR element, the output of the first OR element is connected to a single trigger input, a group of n comparison circuits is entered, with a group of bit outputs of each i-ro the priority register is connected to the first group of inputs of the i-th comparison circuit of the group, the second groups of inputs of the circuits

group comparisons are connected to the group of outputs of the counter, the output of each i-th group comparison circuit is connected to the second input of the i-ro element AND group, the outputs of the AND group elements are connected to the inputs of the second OR element and the information output group of the device, the output of the second OR element is connected to the first input of the element And with the zero input of the trigger, the second and third inputs of the element And are connected respectively to the trigger output and to the output of the pulse generator, the output of the first element OR is connected to the control input of the counter, the output of the element And connected to the information input of the counter.

The drawing shows the device, the structural scheme.

The device contains the register 1 of the order, the group of information inputs 2 devices, the registers 3 priority groups, groups of code inputs 4 devices, elements AND 5 groups, element OR b / counter 7, generator 8 pulses, trigger 9, circuit comparison 10 groups, element AND 11, the OR element 12, the device start input 13, the device response input 14.

The device works as follows.

Signals-requests from subscribers are received through the information inputs of 2 devices in register 1 of the application, the number of bits of which is equal to the number of subscribers. Subscriber priority codes for groups of inputs 4 are received in the corresponding priority registers 3. Note that the highest priority corresponds to the smallest (in the case of a sum counter) or the highest (in the case of a subtracting counter) code.

The initial start signal from input 1 through the OR 12 element enters the control input of counter 7 and resets it to the zero state. The same signal, arriving at a single input of control trigger 9, sets it to unity. The zero signal from the zero output of the trigger 9 is fed to the input of the element 11 and prepares its opening. Since the counter 7 is in the zero state, and priority registers on the priority registers 3, the outputs of the comparison circuits 10 will generate zero signals which, through the AND 5 elements and the OR 6 element, enter the input of the AND 11 element and allow The signals from the generator output 8 pulses to the counting input of the counter 7. As a result, codes 7 are sequentially formed in the counter 7, starting from the minimum and ending at the maximum. When the code at the outputs of the counter 7 coincides with the code in any priority register 3, a single signal is generated at the output of the corresponding comparison circuit 10, which, through the AND 5 element, is opened at the second

At the input one, a single signal of the corresponding register bit 1 of the order arrives at the corresponding output 15 of the device, initiating the beginning of service of the corresponding subscriber, and through the element. OR 6 is fed to the zero input of the control trigger 9, setting it to the zero state, and to the input of the element 11, closing it and thereby stopping the flow of signals from the generator output 8 pulses to the input of the counter 7. Single signal from the zero output of the trigger 9 control enters the input of the element 11 and also prohibits the arrival of pulses from the generator 8 to the counter 7. After the end of the service of the corresponding subscriber, the response signal sets to the zero state through the information inputs 2 the corresponding register tra 1 requisition thereby relieving the queue for service herein by the respective subscriber. At the same time, the same signal through input 14 and the OR element 12 is fed to the single input of the control trigger 9, set it to one, and to the input of the counter 7, set it to the zero state. Next, the cycle of operation of the device is repeated,

The use of the invention reduces the amount of equipment and increases the reliability of the device.

Claims (2)

1. Author's certificate of the USSR 506854, cl. G 06 F 9/18, 1976, 2. USSR author's certificate  475622, class G 06 F 9/18, 1975 (prototype).