SU1200388A1 - Device for generating pulse sequences - Google Patents

Description

The invention relates to measuring equipment and is intended for the formation of reference signals in the control devices of telephone and telegraph communication and data transmission.

The aim of the invention is to expand the functionality of the device by ensuring the installation of modes for the values of the weights and the pulse coefficient.

Fig. I presents a functional diagram for the formation of pulse sequences; Fig.2 is a functional block diagram of the multiplication of the number of clock pulses; Fig. 3 is an example of execution of a controlled pulse shaper.

A device for forming pulse sequences contains (Fig. 1) a clock pulse generator 1, a clock pulse multiplying unit 2, a software block 3, a first ten-day counter 4, a second ten-day counter 5, first 6 and second 7 code comparison blocks, elements 8 and 9 the ban, trigger 10, differentiating chains 11 and 12, the element And 13, the element OR 14.

The generator 1 clock pulses connected to the clock inputs of the block 2 multiplying the number of clock pulses and decade counter 4. The output of block 2 multiplying the number of clock pulses is connected to the clock input of the ten-day counter 5. The first information inputs of blocks 6 and 7 of the code comparison are connected to the code outputs of the decade counters 4 and 5, and the second information inputs - with the corresponding information output1

dami program block 3. The outputs of blocks 6 and 7 comparison codes, respectively, are connected to the first inputs of the elements 8 and 9 of the ban, their outputs

5 is connected to the installation inputs of the trigger 10, the direct output of which is connected to the input of the differentiating circuit 11 and the second input of the prohibition element 8, and the inverse output to the input of the differentiating circuit 12 and the second input of the prohibition element 9. You 'move the differentiating circuit 11 is connected to the first input of the element OR 14, and the output of the differentiating circuit 12 is connected through the element AND 13 to the second

the input element OR 14, the output of which is connected to the installation inputs of the decade counters 4 and 5. The corresponding control outputs of the software block 3 are connected to the second input of the AND 13 element and the control input of the block 2 multiplying the number of clock pulses, the information inputs of which are connected to the corresponding

25 outputs of the program block 3.

Block 2 multiply the number of clock

The pulses comprise (FIG. 2) a frequency multiplying node 15, delay lines 16, counters 17, controlled impulses of the pulse series 18, the element OR 19, the AND-OR element 20 and the inverter 21.

The clock input unit 2 is connected to the input of the node 15 multiplying the frequency and

35 by the first input of the second element AND of the AND-OR element 20. The output of the node 15 is connected to the clock input of the first of the counters 40 of the 17 connected in series through the delay lines 16, the outputs of which are

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connected to the first information inputs of the corresponding t controlled pulse formers 18 series of pulses, the second information inputs of which are the information inputs of block 2. The outputs of the controlled former 18 are connected to the first inputs of the element OR 19, the output of which is connected to the first input of the first element AND of the AND-OR 20 The control input of the block 2 of the element And is connected directly with the second input of the first element And through the inverter

21 with the second input of the second element AND element J-OR 20, the output of which is the output of block 2.

A controlled pulse shaper can be implemented (Fig. 3), for example, on elements I.

22 and 23, the element OR 24, the trigger 25, the short pulse shaper 26 and the inverter 27.

The first inputs of the And 22 elements are the first information inputs of the controlled driver 18, and the second inputs of the And 22 elements are the second information inputs of the controlled driver 18. The outputs of the AND elements 22 through the OR element 24 are connected to the clock input of the trigger 25, the installation input of which is connected to the first input of the first element 22. The first input of element 23 is connected to the direct output of the trigger 25, the second input through the short pulse shaper 26 is connected to the clock input, and the third input through the inverter 27 is connected to zero vyma discharge of the second information input controlled driver 18.

Program block 3 consists of four groups of switches: using the first group of switches, the mode of operation is selected, and the operation of block 2 of multiplying the number of clock pulses and And 13 is controlled, the second, third and fourth group of switches sets the codes of the numbers to the information inputs blocks 6 and 7 code comparison and block 2 multiplying clock pulses.

The device operates in the following five modes: period - duty cycle; period - pulse coefficient; period - impulse; period - interval; period - delay.

Depending on the set operating mode, software block 3 forms output signals that carry information about the multiplication resolution.

5 the number of clock pulses by the multiplication unit, the codes of numbers for the code comparison blocks and the set value of the multiplication factor of the number of clock pulses.

, 0 In the mode of setting the duration of the period T and the value of the duty cycle, software block 3 transmits to the information inputs of blocks 6 and 7 of the code comparison, the number code, respectively

15 of the duration of the repetition period, to the control inputs of the block 2 of multiplying the number of clock pulses - the code of the number corresponding to the duty cycle value allows

₂ θ multiplication operation unit 2 and the multiplication does not permit passage through the gate AND 13 the signal from the differentiating circuit 12. In this case, the input of a first decade counter 4 to ₂₅ are given from the clock generator 1, the repetition frequency of which is chosen from the condition of ensuring the required accuracy of setting the duration pulse sequence. The input of the second decade counter 5 serves clock pulses from the output of block 2 multiplying the number of clock pulses, the number of which per unit of time exceeds 0. times the number of clock pulses from the output

35 of generator 1. At the output of blocks 6 and 7 of comparison, signals of equality of codes appear at those points in time when decade counters 4 and 5 count the number of pulses equal to the code of the number corresponding to the duration of the period T. The signals of equality of codes through elements 8 and 9 of the prohibition arrive at trigger trigger inputs 10. Output signal

⁴ 5 block 6 code comparison calls. setting trigger 10, in which the output pulse appears on the direct output of trigger 10, trigger 10 is turned on, a signal is generated

50 at the output of the differentiating circuit 11, passing through the OR 14 element and arriving at the installation inputs of decade counters 4 and 5. At the same time, counters 4 and 5 are reset and start counting the pulses. The first one counts the number of pulses corresponding to the repetition period of the pulse sequence T, decade

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5 1200388

counter 5, since its input receives pulses with greater frequency.

The signal from the output of the code comparison block 7 through the prohibition element 9 triggers the trigger 10, while the output pulse disappears at the direct output of the trigger 10, a signal appears at the output of the differentiating circuit ^. The signal passing through the And 13 element is prohibited.

When the decade counter 4 counts the number of pulses corresponding to the period T, then the trigger 10 will turn on again, which again will reset the counters 4 and 5.

Thus, the trigger 10 with a repetition period T changes its state, and is in the switched on state by a factor of less time compared to the duration, the period, since the number of clock pulses counted by counters 4 and 5 is the same, and to the input of counter 5 for a unit of time comes in 10 times more pulses than at the entrance of counter 6.

In the case when the set value of the duty cycle exceeds the number 2, then between the first pair of pulses at the output of the code comparison unit 6 several pulses may appear at the output of the code comparison unit 7. However, the prohibition element 9 prohibits the passage of all pulses, except the first. Further process repeats.

Thus, the output of the trigger 10 is provided by forcing a pulse sequence with a repetition period T and a duty cycle of O.

In the mode of setting the period duration and the value of the pulse factor K £, program block 3 transmits to the information inputs of blocks 6 and 7 of code comparison a code of the number corresponding to the repetition duration, to the control inputs of block 2 of multiplying the number of clock pulses a code of the number ensuring the formation of a pulse sequence with a repetition period T and the magnitude of the pulse coefficient Kp allows the multiplication operation to block 2 multiplying the number of clock pulses and prohibits the passage through the element And 13 of the signal from diff Differentiating circuit 1 2.

At the same time, similarly to the previously described mode, the input of the first

the decade counter 4, clock pulses are delivered — pulses from generator 1, the repetition rate of which is chosen from the conditions for ensuring the required accuracy

₅ settings for the duration of the pulse sequence. The input of the second decade counter 5 serves clock pulses from the output of block 2 multiplying the number of clock pulses,

10 the number of which per unit time exceeds the number of clock pulses from the generator output 1 A times, where A is determined from the expression

A = 1 + K, (1,

£ 15

since the input of counter 5 per unit of time comes in (1 + K ^) times more pulses than at the input of counter 6, trigger 10 changes its state with a period T, and is in the on state, forming an output pulse in time.

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thirty

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The time during which the trigger 10 is in the off state, forming the interval between pulses, is ’

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1 + K

(3)

At the same time ^ from ^ feeling

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those. at the output of the trigger 10, a pulse sequence is formed with a repetition period T and a pulse coefficient K £.

In the mode of setting the period and pulse durations, the software unit 3 provides data on the set period duration to the inputs of the code comparison unit 6, and about the set pulse duration to the inputs of the code comparison unit 7, the multiplication factor of unit 2 is set to 1 (the multiplication is prohibited and allowed passing the signal through the element OR 14 only from the output of the differentiating circuit 11. In this mode, the nominal frequency of clock pulses is sent to decade counters 4 and 5. At the time of the trigger activation pa .30 both decade counters 4 and 5 impulse from the output of the element OR are set to the zero position and start

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counting pulses. Potentials from the output of the trigger 10 is prohibited to pass them-. -pulses by the prohibition element 8 and is permitted by the element 9. The first (after counting the number of pulses corresponding to $ of the set pulse duration) forms the output pulse of the code comparison block 7. This impulse, passing through the prohibition element 9, turns off the trigger 10. Further, although the pulses at the output of the comparison unit 7 may occur, they are not passed by the prohibition element 9 and do not affect the trigger 10. After the countdown, the counter 4 _{ί5 by the} number of pulses corresponding to the specified duration of the period, the output pulse of the block 6 comparison codes through the element 8. · prohibition includes a trigger 10, ₂ o

the output of which is formed pulse sequence with the established durations of the period and pulse. Further process repeats. ₂₅

In duration setting mode

and the pulse interval between the pulses software unit 3 provides delivery information specified interval duration to inputs Bloch 6 ₃₀ Single comparisons kodovob set pulse duration - by: comparator unit 7 outputs, establishes unity factor 2 multiplication unit multiplying the number of clock pulses and under transit permits ^ 5 waiting for the signal from the outputs of the differentiating circuits 11 and 12 through the element And 13. In this mode, the counters 4 and 5 receive the nominal frequency of clock pulses, both counters 4 and 5 with the pulse from the output of the elec nta OR 14 is set to the zero position and start counting the clock pulses. At this point, the trigger I0 is turned on and the formation of a pulse begins. The potentials from the output of the trigger 10 allow the passage of a pulse generated by the block 7 comparison code, and accordingly, prohibit the passage of a pulse from the output ^{50 of the} block 8 to the input of the trigger 10. This pulse trigger 10 is turned off. Differentiating circuit 12 generates pulses with which both counters 4 and 5 are again set to the zero position. The trigger 10 is turned on by the output pulse of the code comparison block 6. Further process repeats.

The setting mode of the period duration and the magnitude of the delay is implemented similarly to the mode of setting the duration of the period and pulse described above and differs in that the output signal is taken from the opposite shoulder of the trigger 10.

Unit 2 multiplying the number of clock pulses (figure 2) works as follows.

Node 15 multiplying the frequency multiplies the frequency of the input pulses by the number n, the most significant bit of which is greater than or equal to the high order of the maximum number M by which it is necessary to multiply the number of clock pulses, and the rest of which have zeros.

The counter 17 divides this frequency by the value. K, corresponding to the capacity of the counter. Managed driver 18 series of pulses allocates from each K input pulse counter a series of pulses from zero to K, the number of which corresponds to the number code on the control inputs of the nodes connected to the driver.

The element OR 19 summarizes the pulses coming from all drivers 18. For this, the constant delay times are chosen so that the output of the element OR 19 does not overlap the pulses generated on one driver 18 with the pulses generated on the other drivers 18 arriving at the inputs element OR 19.

The capacity of the first counter 17 (in order of location from the frequency multiplying node to the last driver, the output of which is no longer connected via the delay line to the other drivers) is chosen equal to the value of the most significant digit of η, and the capacities of the other counters 17 are equal to 10.

During the period of pulse repetition at the clock input of the block (input of the frequency multiplying node I5), at the output of the multiplication node, P pulses will be formed. During the same time interval, the output of the first driver can be formed depending on the code of the control signal from 0 to η pulses with a discreteness of installation through 1 10 ^e * ¹ pulses, where C is the number of digits of the number n

Thus, at the output of the element OR 19 for the repetition period input 1200388 10

Depending on the code of the number contained in the control signal of block 2 from 0 to n + 9 -10 ^e * ¹ + 910 ^e * ² + ... +

+ 9 · 10 + 9-10 ^s * ^t . Signals

from the output of the element OR 19 pass to the output of the element AND-OR 20, which is an electronic switch of the output signal of the block. The latter allows the passage of signals from the output of the element OR 19, if there is an enabling signal at the input of the inverter 21. In the absence of an enabling signal at the output of block 2, the input clock pulses of the block pass.

Inverter 21 may be absent in the block circuit, then instead of the signal taken from its output, it is necessary to additionally give an external signal that prohibits multiplication.

Node 15 frequency multiplication can be implemented, for example, according to the scheme of extracting multiple harmonics of the input signal and the formation of rectangular pulses.

Shaper 18 operates as follows.

The trigger 25 is activated on the installation input by a signal at the first output of the counter, and is turned off by cutting the pulse coming from the output.

5 of the element OR 24. The pulse at the output of the element OR 24 appears when the input of the element OR 25 of a signal from the output of the counter 17 through one of the elements AND 22.

10 Setting the required multiplication factor is carried out by the program block for connecting the permitting signal (control input of the multiplication unit) to one of the control ones.

, 5 elements and 22.

So, if the multiplication factor

is equal to seven, then the control signal is fed to the second input only of the element And 22, whose first

20 input is connected to the seventh output of the counter 17.

The trigger 25 is in the on state from the moment the pulse appears on the first output until

25 end of the seventh input pulse,

During the cocked state of the trigger 25 shaper series of pulses at the output passes a number. pulses equal to the number of the _30th multiplication factor in the given digit.

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Claims (3)

1. DEVICE FOR FORMATION OF PULSE SEQUENCES ₄ containing a clock generator, the first decade counter, the counting input of which is connected to the output of the clock generator, the first code comparison unit, the first information inputs of which are connected to the first information outputs of the program block, trigger and the OR element, characterized by the fact that, in order to expand the functionality of the device by providing the ability to work in duty cycle modes and a pulse coefficient, a unit for multiplying the number of clock pulses, a second decade counter, and a second comparison unit, co-, are introduced into it. Dov, two prohibition elements, element And and two differentiating circuits, with the clock input of the clock multiplication unit connected to the output of the clock generator, information inputs connected to the second information outputs of the program block, the control input connected to the first allowing output of the latter, and output connected to the counting input of the second decade counter, the code outputs of which are connected to the first information inputs of the second code comparison unit, the second information inputs of which connect They are connected to the third information outputs of the program block, the outputs of the code comparison blocks are connected via the first and second elements, respectively, to the setup inputs of the trigger, the outputs of which are the device outputs, the forward trigger output is connected to the input of the first differentiating circuit and the second input of the first prohibition element, the inverse output the trigger is connected to the input of the second differentiating circuit and the second input of the second prohibition element, the output of the first differentiating circuit is connected to the first input of the OR element, the output one second differentiating circuit is connected through element I to the second input of the element OR, the second input of element I is connected to the second permitting output of the program block, the output of the element OR is connected to the installation inputs of decade counters, the second information inputs of the first block of code comparison are connected to the code outputs of the first decade counter . 2. The device according to claim 1, in which the multiplying unit of the number of clock pulses contains a node multiplying the frequency of the input signal, the input of which is the clock input of the block, and the output is connected to the clock input of the first of t connected in series through the lines delays of counters, the outputs of the digits of each of the counters are connected with the first information 5 C „„ 1200388 1200388 the inputs of each of the nc controlled pulse formers of a series of pulses, the outputs of all controlled formers of a series of pulses are connected to the inputs of the main input element OR, the output of which is connected to the first input of the first element AND ANDOR element, the second input of which is connected to the control input of the multiplication unit the number of clock pulses, the control input is connected via an inverter ί with the first input of the second element AND of the OR-OR, the second input of which is connected to the clock input of the clock multiplication unit, the output of the AND-OR element is the output of the block, and the second information inputs of each of the controlled pulse drivers are the information inputs of the clock multiplication unit impulse sov. one