SU1150738A1 - Pulse burst generator - Google Patents

Abstract

PULSE FORMER PULSES, containing a pulse generator, a software block, two controlled frequency dividers, a trigger and an element, the first input of which is connected to the output of the first controlled frequency divider, and the second input is connected to a single output of the trigger, the zero output of which is connected to the input of a software unit, the first group of outputs of which is connected to the bit inputs of the first controlled frequency divider, the second group of outputs is connected to the bit inputs of the second controlled frequency divider, the output of which The oho is connected to the zero input of the trigger, the output of the pulse generator is connected to the counting input of the first controlled frequency divider, characterized in that, in order to reduce the device recovery time to its original state and extend the functionality by increasing the number of controlled pulse parameters in the stack, He entered a synchronizer, two elements OR, the second trigger, the second element And and the third controlled frequency divider, the input of which is connected to the output of the second element And, and the output - with zero m input of the second trigger, a single input of which is connected to the output of the first element OR, and a single output of the second trigger is connected to the first input of the second element AND, the second input of which is connected to the output of the pulse generator and the first input of the synchronizer, the first output of which is connected to the installation inputs of the first, the second and third controlled frequency dividers, a single input of the first trigger and the first input of the first OR element, the second input of which is connected to the output of the first element AND, C and the first input the second OR element, the second input of which is connected to the second output of the synchronizer, and the output is connected to the counting input of the second controlled frequency divider, the third group of outputs of the program block is connected to the discharge inputs of the third controlled frequency divider, while the second synchronous input terminal is connected to the output of the program block. OS

Description

The invention relates to a pulse technique and can be used in devices for automation, control, monitoring and diagnostics.

A pulse train shaper is known that contains a pulse generator, a coincidence element, a trigger and a comparator, some inputs of which are connected to the outputs of the program block, other inputs are connected to the counter outputs, and the output is connected to the trigger reset input, which is connected with counter input 1.

A disadvantage of the known driver is the limited functionality due to the fact that the code of the sequence number of a pack is not associated with any of its bits with the parameters of the generated pulse train, which eliminates the possibility of flexible control of the parameters of the packet. the number of times to increase the full set of formed packs, it is required to increase the memory size and the number of output tires by the same amount, and also to increase the counter size and frequency accordingly. comparator that determines an insufficient amount actuated packs pulse parameters.

The closest technical solution to this invention is a pulse driver that contains a pulse generator, a coincidence element, a trigger and a second controlled frequency divider, some inputs of which are connected to the outputs of the program block, other inputs connected to the outputs of the Counter, and the output connected to the reset input trigger, the direct output of which through the element I is connected with the input of the counter, the first controlled frequency divider, the inputs of which are connected to the additional outputs of the program block, the counting input with dinene with a pulse generator, the reset input is connected to the output of the second controlled frequency divider and the reset input of the counter, and the output is connected to another input of the I element, and the inverter, whose input is connected to the output of the first controlled frequency divider, and the output is connected to the trigger installation input The inverse output of which is connected to the control input of the program block 2.

The disadvantages of this device are low speed at low pulse frequency in a burst due to an increase in its availability for operation at these frequencies and limited functionality due to the lack of control of the pulse ratio in the burst.

The purpose of the invention is to reduce the recovery time of the device to its original state and to extend the functionality by increasing the number of

controlled parameters of pulses in a pack by controlling the duty ratio of pulses in a pack.

The goal is achieved by the fact that a pulse generator that contains a pulse generator, a program block, two controllable frequency dividers, a trigger and an element, whose first input is connected to the output of the first controlled frequency divider, and a second input with a single trigger output, is zero. the output of which is connected to the input of the program block, the first group of outputs of which is connected to the bit inputs of the first controlled frequency divider, the second group of outputs is connected to the bit inputs of the second controlled elitel frequency, the output of which is connected to the zero input of the trigger pulse generator output is connected to the zero input of the trigger pulse generator output is connected with a countable

0 input of the first controlled frequency divider, entered a synchronizer, two elements OR, the second trigger, the second element AND and the third controlled frequency divider, the input of which is connected to the output of the second

5 And, and the output with zero input of the second trigger, a single input of which is connected to the output of the first OR element, and a single output of the second trigger is connected to the first input of the second And element, the second input of which is connected to the output

0 pulse generator and the first input of the synchronizer, the first output of which is connected to the installation inputs of the first, second and third controlled frequency dividers, a single input of the first trigger and the first input of the first OR element,

The second input is connected to the output of the first element AND and the first input of the second element OR, the second input of which is connected to the second output of the synchronizer and the output to the counting input of the second controlled frequency divider, the third group of outputs of the program block is connected to the bit inputs of the third controlled frequency divider, while the second input of the synchronizer is connected to the output of the program block.

FIG. 1 shows the structural scheme of the pulse builder; in fig. 2 is a block diagram of the first, second and third controlled frequency dividers; in fig. 3 - synchronizer block diagram; in fig. 4 - block diagram of the program block.

The shaper pulse generator (Fig. 1) contains a pulse generator 1, program block 2, first 3, second 4 and third 5

5 frequency dividers, the first 6 and second 7 triggers, the first 8 and second 9 elements And, the first 10 and second 11 elements OR, the synchronizer 12.

The pulse shaper driver has an output bus 13.

The output of the pulse generator 1 is connected to the counting input of the first 3 frequency divider, the second input of the second 9 element And and the first input of the synchronizer 12, the first output of which is connected to the zero setting inputs of the first 3, second 4 and third 5 frequency dividers, the single input of the first 6 trigger and the first entry of the first 10 elements OR. The first group of outputs of the program block 2 is connected to the corresponding inputs of the first 3 frequency dividers, the second group of outputs - with the corresponding inputs of the second 4 frequency dividers, and the third group of outputs - with the corresponding inputs of the third 5 frequency dividers. The output of the first 3 frequency divider is connected to the first input of the first 8 element I, the second input of which is connected to the single output of the first 6 trigger, and the output to the inputs of the first 10 and second 11 elements OR, the second input of which is connected to the second output of the synchronizer 12. The output of the first 10 element OR is connected to a single input of the second 7 trigger. The output of the second 11 element Or connected to the counting input of the second 4 frequency divider, the output of which is connected to the zero input of the first 6 trigger whose output is connected to the input of software block 2. The output of the second element And 9 is connected to the counting input of the third 5 frequency divider, the output of which is connected to zero input of the second 7 trigger, a single output of which is connected to the input of the second 9 element And and the output thickness 13 of the device.

The frequency divider (Fig. 2) contains the comparator 14, the counter 15, the element OR 16.

The frequency divider has the first 17 and second 18 input tires, a group of input fields 19.1 ... 19.P and an output busbar 20.

The synchronizer (Fig. 3) contains the first 21, second 22, third 23 and fourth 24 D-triggers, the element NOT 25, the first 26 and the second 27 elements I.

The synchronizer has the first 28 and second 29 input lines and the first 30 and second 31 output tires.

The program block (Fig. 4) contains the first 32, second 33 and third 34 registers, the first 35, the second 36 and the third 37 And groups of elements, And 38 elements.

The program block has the first 39 and second 40 input buses and the first 41, the second 42 and the third 43 groups of output lines, the output busbar 44.

The device works as follows.

The generator 1 generates rectangular pulses of a sufficiently high constant frequency, equal, for example, to the maximum frequency of operation of the logic elements of the pulse generator.

From program block 2 to the first frequency divider 3, the selection code often arrives, pulses, to the second frequency divider 4 - the code of the number of pulses in the packet, and to the third frequency divider 5 - the code of the pulse duration in the packet.

Formation of a series, i.e. bursts of pulses begins on the control signal with

 software block 2, which is fed to the second input of the synchronizer 12, the first input of which receives pulses from the output of the generator 1. After a time of 141.5 T,

5 where T is the pulse following period from the output of generator 1, a single pulse of 0.5 T duration is generated at the first output of synchronizer 12, which is delayed relative to the corresponding pulse from the output of generator 1 by 0.5 T. Time

The occurrence of a single pulse is counted from the leading edge of the control signal from program block 2. To simplify the time relationships, it is assumed that generator 1 forms a periodic sequence of pulses with a duty cycle of 2.

A single pulse from the output of the synchronizer 12 sets the first 3, second 4 and third 5 frequency dividers to the zero state and the first 6 to the single state

0 and second 7 flip-flops (second 7 flip-flop is set to one state by a single pulse from the output of synchronizer 12 through the first 10 elements OR). A high level signal from a single output of the second 7 trigger enters the output bus

5 13 devices and opens the second element 9, connecting the output of the generator 1 with the counting input of the third 5 frequency divider. A high level signal from a single output of the first 6 trigger opens the first 8 element

0 AND, connect the output of the first 3 frequency divider with the single input of the second 7 trigger (through the first 10 element OR) and the counting input of the second 4 frequency divider (through the second 11 element OR).

After a time t 0.5 T from the beginning of the appearance of a single pulse, a single pulse with a duration of 0.5 T is formed at the second output of the synchronizer 12, which through the second 11 element OR is fed to the counting input in the 4th frequency divider and switches it to the next state, fixing the formation of the device of the first pulse of the stack. The pulses from the output of the generator 1 are fed to the counting input of the third 5 frequency divider, which compares the code of the pulse duration in a pack given by the program block 2 with the number of incoming pulses. At the moment of comparing the set and current codes, a pulse is generated at the output of the third 5 frequency divider, which switches the second 7 flip-flop to the zero state, which closes the second 9 AND element, disconnecting the output of the generator 1 from the count input of the third 5 frequency divider. Simultaneously with the switching of the second 7 flip-flop, the third 5 frequency divider is reset (Fig. 2).

The high level signal, which is formed on the unit output of the second trigger as a result of switching the latter from zero to one and vice versa, goes to the output bus 13 of the device and represents the first pulse of the stroke with a given duration.

The first 3 frequency divider divides the frequency of the pulses from in, the output of the generator 1 in accordance with a given program block

2 frequency selection code, which results in the selection of the required frequency of pulses in the pack. Impulses from the output of the first

3 frequency dividers through the open first 8 element And arrive at the counting input of the second 4 frequency divider (through the second 11 element OR) and the single input of the second 7 trigger (through the first 10 element OR).

High level signals from the single output of the second 7 trigger come to the output bus 13 of the device, and also open the second 9 element I, connecting the output of the generator 1 to the counting input of the third 5 frequency divider. The pulses from the output of the generator 1 are fed to the counting input of the third 5 frequency divider, which compares the code of the pulse duration in a packet given by the software block 2 with the number of incoming pulses. At the moments of comparing the set and current codes, pulses are generated at the output of the third 5 frequency divider, which switch the second 7 flip-flop to the zero state.

The pulses from the output of the first 3 frequency dividers also go to the counting input of the second 4 frequency dividers. The second 4 frequency divider is filled with pulses arriving at its counting input until the code of the number of pulses in the packet specified by the software block 2 compares with the current code. At the moment of comparing the set and current codes, a pulse is generated at the output of the second 4 frequency divider, which switches the first 6 flip-flop to the zero state, which closes the first 8 AND element, disconnecting the output of the first 3 frequency divider from the counting input of the second 4 frequency divider and single second input 7 trigger. The high signal from the zero output of the first 6 trigger enters the input of software block 2 and allows the latter to change the codes on the inputs of the first 3, second 4 and third 5 frequency dividers (if necessary) and call the next batch of pulses

by generating a control signal at its output.

The controlled frequency divider (Fig. 2) works as follows.

The input bands 19.1 ... 19.P from program block 2 receive a code proportional to the required division factor. The input bus 17 receives impulses from the generator output, as a result of which the counter 15 is filled until the comparison with the comparator 14 acting on the input channels 19.1 ... 19.P code with the current code in the counter 15. At the time of comparison the codes on the output bus 20 are formed pulses that simultaneously arrive at the Zero installation input of the counter 15 (through the element OR 16) and nullify the latter, after which the described cycle of operation of the frequency divider is repeated. The input bus 18 serves to allow the counter 15 to be reset by a signal from the outside.

Synchronizer (Fig. 3) works as follows.

The input bus 28 receives pulses from the output of the clock generator, and the input bus 29 receives the control signal from the program block. The first 21 D-flip-flops serve to tie the control signal to the clock pulses. After the first 21 D-flip-flops are switched to one state, the third 23 D-flip-flops are switched to one state. Next, the second 22 D-flip-flop and the fourth 24 D-flip-flop are switched to one state. The switching of the third 23, second 22 and fourth 24 D-flip-flops from the zero to one state occurs sequentially one after the other after every half-period of the following clock pulses. As a result of switching these D triggers on the first 30 and second 31 output wounds, single pulses are generated with a half-cycle duration of following clock pulses. In this case, the first single pulse is formed during the absence of a pulse in a periodic sequence of pulses, and the second single pulse is delayed relative to the first one by half the cycle of the following clock pulses. After the termination of the control signal on the input busbar 28, the first 21, third 23, second 22 and fourth 24 D-flip-flops switch to the zero state, returning the synchronizer to the initial state.

The first single pulse of the synchronizer serves to set to zero the state of all frequency dividers of the pulse builder, and at the same time it is used to form the first pulse in the packet. The second single pulse serves to start counting the number of pulses in a packet.

The program block (Fig. 4) works as follows.

From the computer to the input bus 39 receives a code for selecting the frequency of the pulses, the code of the number of pulses in the packet and the code for the duration of the pulses in the package.

A high level signal is supplied to the input bus 40, which permits the writing of the indicated codes to the first 32, second 33 and third 34 registers through the open elements AND first 35, second 36 and third 37 groups. After writing the codes, the control signal is fed to all registers from the computer to the input bus 40, which is fed to the output bus 44 through the open element 38. A series formation begins on this signal, i.e. burst, the proposed device.

In comparison with the known device in the proposed invention, at low pulse setting frequencies in a bundle, the device recovery time to the initial state is reduced from

ii К- Т

in a known device up to a value of t241.5 T,

in the proposed device

where T is the pulse following period on

clock output; K - the division factor of the divider

clock frequency, and has more functionality due to the use of pulse duty ratio control in a burst.

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Claims (1)

A PULSE FORMER comprising a pulse generator, a program unit, two controllable frequency dividers, a trigger, and an I element, the first input of which is connected to the output of the first controllable frequency divider, and the second input is connected to a single output of the trigger, the zero output of which is connected to the input of the program unit, the first group of outputs is connected to the bit inputs of the first controlled frequency divider, the second group of outputs is connected to the bit inputs of the second controlled frequency divider, the output of which connected to the zero input of the trigger, the output of the pulse generator is connected to the counting input of the first controlled frequency divider, characterized in that, in order to reduce the recovery time of the device to its original state and expand the functionality by increasing the number of controlled parameters of the pulses in the packet, synchronizer, two OR elements, a second trigger, a second And element, and a third controllable frequency divider, the input of which is connected to the output of the second And element, and the output - with a zero input horn trigger, the single input of which is connected to the output of the first element OR, and the single output of the second trigger is connected to the first input of the second element And, the second input of which is connected to the output of the pulse generator and the first input of the synchronizer, the first output of which is connected to the installation inputs of the first, second and third controlled frequency dividers, a single input of the first trigger and the first input of the first OR element, the second input of which is connected to the output of the first AND element, and the first input of the second OR element, whose input is connected to the second output of the synchronizer, and the output is connected to the counting input of the second controlled frequency divider, the third group of outputs of the program unit is connected to the discharge inputs of the third controlled frequency divider, while the second input of the synchronizer is connected to the output of the program unit. S! „„ 1150738