SU1554115A1 - Device for shaping code sequences - Google Patents

Abstract

The invention can be used in automatic data processing systems. The goal is to increase the information content of the generated code sequence. A device for generating code sequences generates multi-bit code sequences at known time intervals ΔT between adjacent switching outputs of the device and assigned them to code groups of switching device outputs (channels), and the intervals ΔT are measured both in ticks and γ times large units. The device contains a pulse generator 2, D-flip-flop 3, element AND 5 and elements OR 1 and 18, performing initial setup, starting and stopping the device, frequency divider 7, delay element 10 and pulse counter 17, measuring time intervals ΔT, counters 8 and 9, organizing access to memory blocks 11 and 13, which store, respectively, time interval codes ΔT and the corresponding groups of channel number codes, comparison block 20, which detects the clock preceding the switching of device outputs, short pulse 4 drivers and 16 and trigger 6, which read the channel number code group from memory block 13 through register 19 to the inputs of the demultiplexer 21, which converts information into unitary codes. These codes, by single values, invert the states of the input T-flip-flops of the block 22 of the code-forming channels, which, when the next cycle arrives, communicate their values to the output D-flip-flops of the block 22 and, accordingly, the device outputs. The block 13, the frequency divider 12 and the switch 15 provide the counting of the intervals ΔТ in γ cycles, which increases the information content and leads to a decrease in the memory size of the block 11. 1 Il.

Description

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a group of channel number codes from memory block 13 through register 19 to the inputs of the demultiplexer 21, which converts information into unitary codes. These codes, by single values, invert the states of the input T-flip-flops of the block 22 of the code-forming channels, which, when the next cycle arrives, communicate their values to the output D-flip-flops of the block 22 and, accordingly, the device outputs. Block 13, frequency divider 12 and switch 15 provide the counting of intervals At in f cycles, which increases the information content and leads to a decrease in the memory size of the block 11, 1 or 0

The invention relates to a pulse technique and can be used in automatic data processing systems.

The drawing shows a functional diagram of an apparatus for generating a code sequence.

The purpose of the invention is to increase the information content of the generated code sequence due to its reproduction within wide limits.

The drawing shows a diagram of the device.

The device contains the first element OR I, the generator of 2 pulses, D-flip-flop 3, the first driver 4 short pulses, the element And 5, RS-flip-flop 6, the first frequency divider 7, the first counter 8 addresses, the second counter 9 addresses, delay element 10, first memory block 11, second frequency divider 12, second memory block 13, third memory block 14, switch 15, second shaper 16 short pulses, pulse counter 17, second OR 18 element, register 19, block 20 comparison, demultiplexer 21, block 22 of code generation channels, start bus 23, bus 24 stop, w Inu 25 of the initial installation, the output bus 26. The first input of the element OR 1 is connected to the bus 24 stop, the second input - with the output of the higher bit of the counter 8 address, and the output is connected to the R input of the D-flip-flop 3, the synchronous input of which is connected to bus 23 start device, and the output with the first input element And 5, the second input of which is connected to the output of the generator 2 pulses, and the output with the counting input of the counter 9 addresses and the input of the frequency divider 7, the installation input of which is combined with the installation input of the counter 9 addresses , the reset input of the counter 8 address-, in house dump block of 22 channels formiro5

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codes, the first input element OR 18 and is connected to the bus 25 setup. The output of the frequency divider 7 is connected to the input of the delay element 10 whose output is connected to the first information input of the switch 15 and to the input of the frequency divider 12, the installation input of which is connected to the output of the OR element 18, the reset input of the register 19, the setting input of the pulse counter 17, the R input RS flip-flop 6, and the output is connected to the second information input of the switch 15, the output of which is connected to the counting input of the pulse counter 17, to the synchronous input of block 22 and to the synchronous input of memory 14, the output of which is connected to the controlling input m of the switch 150. The information outputs of the pulse counter 17 are connected to the first inputs of the comparison unit 20, the second inputs of which are connected to the outputs of the memory block 11, the address inputs of which are connected to the address inputs of the memory block 14 and the outputs of the address counter 8, the counting input of which is connected to the inverse the output of the RS flip-flop 6, the direct output of which is connected to the resolution enable input of the counter 9 of the address and the input of the memory sample 13, the address inputs of which are connected to the outputs of the counter 9 of the address that controls the output of the memory 13 via The device 16 is connected to the second input of the OR element 18, and the outputs of the memory block 13 are connected to the information inputs of the register 19, the outputs of which are connected to the address inputs of the demultiplexer 21, the outputs of which are from the first to the n and the inverse the control input of the demultiplexer 21 is connected to the inverse output of the comparator unit 20, the direct output of which is connected via the shaper 4

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With the S-input of the RS flip-flop 6, the outputs of block 22 are the output buses 26 of the device o. Each channel of the block 22 of the channel forming codes contains serially connected

T-trigger and D-trigger Channel D-Triggers are channel block outputs.

The device works as follows.

The memory block 11 stores a sequence of time interval codes and t between adjacent switching outputs of the device,

If the time interval At lies within

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Where -p - increased by one the maximum value received by the counter 17; m 2 (a is the counter's size 17; then the time interval At is represented as At At m + At;

& t j; , and in block 11 the values At1 and Atn are stored,

If the time interval is / 3t Ј (jL О, then it is represented at several intervals of type At, having weight y, and interval. For example, at v 16, the time interval At 300 is represented at intervals At 15, At 3 At 12, since 15x16 + 3x16 + 12 300. In block 11, for this case, codes of quantities At are stored.

At 3 and dt 12.

A one-bit memory block 14 stores a sequence of information bits that correspond one-to-one to time slot codes of memory block 11, and for each At and At1 codes the bits take zero and one values respectively. One-to-one correspondence is established by combining the address inputs of blocks 1 1 and 14 memories.

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In memory block 13, groups of i codes (i 1, p) are stored sequentially, each group contains channel number codes for block 22 (or, equivalently, output bus numbers 26), which change their state at time indicated by the corresponding time interval Jt.

If the time interval At is divided into parts, then the entire received interval of type At corresponds to groups consisting of one zero code, and the interval At is assigned a group of codes relating to the entire time interval t. are listed in random order. The channel number code contains an extra bit, which takes in the last code of each group a single value and a zero value in other codes. This indication of the end of a group of codes is read from the control output of memory block 13. Before starting the device with a signal Initial setting, arriving at spike 25, the address counter 9 is reset to zero, channel triggers are set to 22 (output buses 26), divider triggers are set to one value 7 and 12 frequencies and the counter 9 addresses, and through the element OR 18 the register 19 is reset to tulle and shock, RS-trigger b and all the triggers of the counter 170 are set to one value

A trigger pulse arrives through the spike 23 on the D-flip-flop D trigger, sets it to one state (the D-flip-flop information input is powered by the level log. 1), allowing the pulses from the pulse generator 2 to pass through the And 5 element to the counting input of the address counter 9 and through the frequency divider 7 - to the input of the delay element 10. From the output of element 10, the delayed SR pulses, which measure the working cycles of the device, go to the first information input of the switch 15, and through frequency divider 12 to the second information input of the switch 15. The first pulse from the output of the delay element 10 goes to both information inputs of the switch 15 (divider 12 frequency under the action of the first pulse goes into

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the zero state with the output at the output of the SI pulse). In this case, the switch 15, regardless of the value of the signal at the control input, transmits a pulse to the counting input of the counter 17, setting all its triggers to the next zero state. The code from the outputs of the counter 17 is fed to the first inputs of the comparison unit 20. At this time, the memory block 11 reads from the zero address coming from the outputs of the address counter 8, the first code of the time interval t. The same address from the output of the memory block 14 reads Bit B of information that arrives at the control input of the switch 15 and connects the clock signal from the output of the delay element 10 and the clock signal from the output of the frequency divider 12 to the clock output at the same time, the sync signals of the control signal 17 arrive at the counting input 17 operation of the device if the temporary code read interval ut type, SI and clock signals with a repetition frequency in the y times smaller than SI, if the code read temporary type gc interval.

The code from the output of the memory block 11 is delivered to the second inputs of the comparison block 20, which reduces the code value by one low-order unit and compares the result with the counter code 170 If the compared codes match, the signal log. O1 from the inverse output of the comparison unit 20 is fed to the inverse control input of the demultiplexer 21, and a single signal from the direct output of the comparison unit 20 is fed to the driver 40. In this case, a short unit impulse is formed, setting the RS-flip-flop 6 to the single state on the S-input. A single signal from the direct output of the RS-flip-flop b is fed to the sampling input of the memory block 13 and the counting enable input of the address counter 9, which, under the action of the sync pulses arriving at its counting input start changing its state at the address input of memory block 13, the sequence of address values. At these addresses, from the output of block 13, the codes of channel numbers of block 22 are read through register 19 to the address input of demultiplexer 21, ensuring the successive inversion of the states of the corresponding T-flip-flops

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ka 22 channels (through the information inputs block 22 channels).

Simultaneously with reading from the memory unit 13 the last channel code of unit 22, the unit output signal of the group termination is recorded from the control output of the memory unit 13. This signal is fed to the input of the imager 16, from the output of which a short pulse goes through the element OR 18 to the reset input of the register 19, the R-input of the RS flip-flop 6 and to the inputs of the installation of the frequency divider 12 and the counter 17. In this case, the register is reset to 19 In the RS-flip-flop 6 and setting the triggers of the splitter 12 frequency and the counter 17 into one state. The signals from the direct and inverse outputs of the RS flip-flop 6 respectively stop the change of the states of the counter 9 of the address and transfer to the next state the counter 8 of the address. from block Memory 11 reads the following time interval code dt. This code is compared by comparison unit 20 with codes that are replaced at the outputs of counter 17 by the action of the SR or SI clock pulses (depending on the value of the information bit read from the memory block 14).

The next SR sync pulse, appearing at the output of the delay element 10, arrives at the synchro-input of the channel block 22, providing a census of information from its input T-flip-flops to the output D-flip-flops, from the outputs of which the signals generated go to the device buses 26.

If the time interval dc was divided into several intervals, then for each of the 3t type intervals received, a group of codes consisting of one zero code will be read from memory block 13. Under the influence . This code, rewritten to register 19, the demultiplexer 21 changes its zero output, not connected to the information inputs of the channel block 22. Thus, switching on the device buses 26 at the break points of the time interval Ut into parts does not occur.

 With each SI or SI clock pulse appearing at the counting output of counter 7, this counter increases the code value at its output by one. When reaching the code ena 15

, for a unit smaller code value ut (type l t or and t), the comparison unit 20 establishes this fact and the cycle of preparing and changing the values of the signals on the buses 26 (with the arrival of the next corresponding sync signal

The device is terminated when the high-order bit of the address 8 counter is set to a single value. This value goes through the element OR 1 to the R input of the D flip-flop 3, which then goes into the zero state, which prohibits the passage of the pulses of the generator 2 through the element And 5. Shutdown of the device can also be achieved by supplying a single value to the R input D -trigger 3 via bus 24 stops and the item OR 1.

Thus, this device allows time intervals 41 to be counted not only during the device operation cycles, but also by –Y times larger units, which leads to an increase in the information content of the generated code sequence, and also reduces the required memory size of the block 11 for storage At codes for large intervals of time between adjacent switching signals on the output buses of the device

Claims (1)

Invention Formula A device for generating code sequences comprising a pulse generator, first and second elements OR, D-flip-flop, RS-flip-flop, first and second shapers of short pulses, And element, first frequency divider, first and second address counters, delay element, the first and second memory blocks, a pulse counter, a comparison register register, a demultiplexer, a block, code generation channels, the first input of the first element OR is connected to the device stop bus, the second input of the first element OR is connected to the high-order output of the first address counter, and the output is connected to the R-input of the D-flip-flop, the synchronous input of which is connected to the device launch bus, and the output to the first input of the element I, the second input of which is connected to the output of the pulse generator, and the output from the account Q 5 0 50 five Q 5 0 5 1510 the input of the second address counter and the input of the first frequency divider, the setup input of which is connected to the installation input of the second address counter, the reset input of the first address counter, the reset input of the code generation channel block, the first VCO.-. the house of the second element OR is connected to the bus of the initial installation of the device, and the output of the first divider. the frequency is connected to the input of the delay element; the information outputs of the pulse counter are connected to the first inputs of the comparison unit, the second inputs of which are connected to the outputs of the first memory block, the address inputs of which are connected to the outputs of the first address counter, the counting input of which is connected to the inverse output RS-trig —Gera, the direct output of which is connected to the counting input input of the second address counter, the outputs of which are connected to the address inputs of the second memory block, the outputs of which are connected to the information inputs of the register, The outputs of which are connected to the address inputs of the demultiplexer,. the first to nth outputs of which are connected to the corresponding information inputs of the code generation channel block, and the inverse control input of the demultiplexer is connected to the inverse output of the comparator block, whose direct output is connected to the S input of the RS flip-flop, R- through the first short pulse shaper the input of which is connected to the reset input of the register, the installation input of the pulse counter and the output of the second OR element, the second input of which is connected to the output of the second short pulse generator, the input of which is connected with the control output of the second memory block, the outputs of the channel block are output buses of the device, characterized in that, in order to increase the information content of the generated code sequence, a second frequency divider, a third memory block and a switch are entered into it, and the address inputs of the third block the memory is connected respectively to the address inputs of the first memory block, the sync input of the third memory block is connected to the synchronization input of the code generation channel block, the counting input of the pulse counter and the switch output, and Exit - to pack .11155411512 equal input of the switch, the per-output of the second element OR, and you-.  the new information input of which the connection is with the second information input Dinen with output of delay element and switch, direct output of RS flip-flop the input of the second frequency divider, us-connected to the input of the second sample A setting input is connected to a memory unit.