SU1684916A1 - Device for driving package errors - Google Patents

Abstract

The invention can be used in monitoring and diagnostics equipment stands of digital information processing equipment, in particular for digital video recording equipment, and in simulating discrete communication channels. The aim of the invention is to enhance the functionality by generating an error stream with different durations and with its likelihood. To achieve the goal, blocks 6, 10 of memory register 11, a pulse counter 12 and a comparison block 13 are entered into a device for generating packet errors. The device also contains a generator of 1 pseudo-random sequences, a pulse counter 5, registers 7, 8, and a comparison block 9. Blocks 5-10 perform the function of a selector. 1 il.

Description

The invention relates to a pulse technique and can be used in stands for monitoring and diagnosing digital information processing equipment, in particular for digital video recording equipment, as well as in modeling real discrete communication channels.

The purpose of the invention is to expand the functionality by forming an error stream with a short duration and with its likelihood.

The drawing shows a block diagram of a device for generating packet errors.

The device for generating packet errors contains a pseudorandom sequence generator 1 (PRS), performed on the shift register 2 and the element EXCLUSIVE OR 3, the control bus 4, the first pulse counter 5,

the first memory block 6, the first 7 and second 8 registers, the comparison block 9, the second memory block 10, the third register 11, the second pulse counter 12, the second comparison block 13, the clock frequency bus 14, the output bus 15 of the error signal

The input of the PSP 1 generator is connected to the bus 14 to the clock runs of the counter 5, register 11, counter 12, the output of the PSP generator 1 is connected to the control input of the counter 5, the discharge outputs of the PSP generator 1 are connected to the bit inputs of the memory block 6, bit the outputs of counter 5 are connected to the bit inputs of registers 7 and 8, the synchronization inputs of which are connected to the first and second outputs of memory block 6, the third output of which is connected to control flows of the counter 12 and register 11, the bit inputs of which are connected to the outputs of block 10 memory first, second and third of the group

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The dongle of which is connected to the outputs of registers 7 and 8 and bus 4, respectively, and the control input of unit 10 is connected to the first input of the block bis, the output of comparison unit 9, the first and second group of inputs of which are connected to the outputs of registers 7 and 8, the outputs of register 11 are connected to the first group of inputs of the comparison unit 13, the second group of inputs of which is connected to the outputs of the counter 12, the input of which is connected to the outputs of the comparison unit 13 and the second input of the memory block 6, the fourth and fifth outputs of which are connected respectively with their first and second governing inputs.

Counter 5, memory block 6, registers 7 and 8, comparison block 9, and memory block 10 function as a selector.

The device for generating packet errors operates as follows.

Shift register 2, having a length of m bits, is clocked at a fixed frequency fT supplied to its clock input via a clock frequency bus 14. A serial signal is output from the output of the EXCLUSIVE OR 3 element to the input of the shift register 2, which is the sum modulo 2 signals of the nth digit of the shift register 2 arriving at the first input of the EXCLUSIVE OR 3 element and its last (mth) , the bit arriving at the second input of the EXCLUSIVE OR element 3. From the output of the shift register 2 to the control input of the counter 5, a pseudo-random sequence signal arrives. The same signal, but shifted by one, two and three periods of the clock frequency fT, comes from the bit outputs of register 2 to the inputs of block 6. The absence of a signal at the control input of counter 5 corresponds to loading 5 zeros into the counter, and its presence translates counter 5 in the counting mode with a clock frequency fT, arriving at its clock input. At the end of the counting, the value of counter 5 is rewritten into register 7 or 8, depending on the signals received at the clock inputs of these registers, respectively, from the first or second output of memory block 6. Their temporary position is determined by signals from the discharge outputs of the generator SRP 1 to the discharge inputs of memory block 6.

The selection of register 7 or 8 for recording the value of counter 5 is carried out in memory block 6 by the output signal of comparator block 9 arriving at its first input. This signal determines the larger of the values set at the outputs of registers 7 and 8, and into the register in which

the moment of time is fixed a smaller number; the value of the current state of counter 5 is rewritten, which determines the length of a pack of zeroes (ones) in the signal of a pseudo-random sequence. The signal from the output of block 9 is also fed to the control input of memory block 10, which converts the larger of the values set on its first

0 two inputs in the duration of the packet errors. A code corresponding to the length of a bundle of zeros (units) of the duration of the error packet arrives on the control bus 4 to the third inputs of the memory block 10. When a signal arrives from

5, the output of block 9, a signal arriving at the second control input of this memory block, appears at the input of the memory storage block at its fifth output. This signal, together with the signal from the output of block 9, uniquely determines 0 em, whether the new fixed state of counter 5 is greater than its previously fixed value. In this case, at the moment of time determined by the signals from the outputs of the generator SRP 1, on

5, the third output of memory block 6 generates a signal that is fed to the control input of register 11, and the value of the error packet duration set at the output of memory block 10 is copied to register 11. In addition, under the action of a signal from the third output of block 6 arriving at the control input of the counter 12, the counter is loaded zero, which leads to the appearance of an error signal at

5 output of the comparison unit 13. The signal from the output of block 13 is also fed to the control input of counter 12, translates it into counting mode, carried out with a clock frequency, and remains for the entire time until the value at the output of counter 12 coincides in block 13 with the value fixed at the output of register 11. The error signal from the outputs of block 13 is also fed to the input of block 6 of memory. With this in

5 The moment of the end of the error signal at the four-earthed output of block 6, a signal appears, which is fed to the first controlling E.COM IN of this memory block and is used to form the signals controlling the operation of registers 7 and 8.

Thus, the proposed device, E.O., makes it possible to generate an error stream, that is, E. which would contain errors of different durations and each with its own probability of occurrence, and determining the duration of packs of zeros or ones in the SRP signal is carried out by a counter 5, the contents of which are the end of the burst is rewritten to one of two registers 7 or 8. A burst of zeros or units of a certain duration appear with a known probability in the SRP stream. Therefore, when each of these bursts appears in this device, an error signal of such a duration is formed that would correspond to the probability of the occurrence of such a batch in the SRP stream. This conversion of the probability of occurrence of an error (the length of a bundle of zeros in the SRP stream) into the duration of the error takes place in memory block 10, and it is performed with a pre-set and unmodifiable code on control bus 4 during operation. The inter-synchronization of code changes on bus 4 is not required, since the codes on this bus only determine the selection of the correspondence table of error durations to their probability of occurrence, i.e. channel error flow model. Since in a real channel there may be errors of sufficiently long durations, the cause of which are various factors, the problem arises of the formation of overlapping errors of different durations. For this purpose, registers 7 and 8, as well as block 9, are entered into the proposed device.

Claims (1)

Claim device A packet error generator comprising a pseudo-random sequence generator, the input of which is connected to the clock frequency bus and the clock input of the first pulse counter, the first comparison unit, the first and second group of inputs of which are connected to the outputs of the first and second registers, the third register, which differs by the fact that, in order to expand the functionality, the first and second memory blocks, the second pulse counter and the second comparison block are inserted into it, the first and second groups of inputs of which are connected respectively to the outputs of the second pulse counter and the third register, the bit inputs of which are connected to the outputs of the second memory block; the first, second and third groups of inputs of which are connected respectively to the outputs of the first and second registers and to the control bus, the control input of the second memory block is connected to the output of the first block and to the first input of the first memory block, the bit inputs of which are connected to the bit outputs of a pseudorandom generator, the output of which is connected to the control input of the first pulse counter, the outputs of which are connected to the bit inputs of the first and second registers, the clock inputs of which are connected with the first and second outputs of the first block memory, the third output of which is connected to the control inputs of the second pulse counter and the third register, the clock input of which is connected to the clock frequency bus and to the clock the input of the second pulse counter, the input of which is connected to the output bus, to the output of the second comparison unit and the second input of the first memory block, the fourth and fifth outputs of which are connected respectively with their first and second control inputs. Compiled by V. Chizhov Editor A, Veselovska Tehred M. Morgental 15 Ci on / I Errors  h ynaof.-ieHi, a Proofreader S. Cherni