SU1280447A1 - Device for checking the recording channels of magnetic tape recorders - Google Patents

Abstract

The invention relates to an engineering industry, in particular, to a technique of digital magnetic recording, and can be used to ensure the accuracy of the recording channels both in the function control mode and during information recording. The purpose of the invention is to increase the accuracy of control recording channels due to the mutual synchronization of input and recording information. The reference coding unit 9, identical to the information coding units 2, is alternately connected using synchronously operating switches 6 and 7 to the information input and output of the coding unit 2 of the channel selected for monitoring, and the two output signals of these blocks are compared with the adder 15. Registers 11, 12 and modulators 13, 14 modulo two phase out the output signals of the monitored coding unit 2 and the reference coding unit 9, which are identical in information content. The output signal is the sum (L of the Torah 15 modulo two is gated with a clock sync signal on the element I 16, at the output of which error pulses are formed, counted by the pulse counter 17. 2 ill. To 00 about 4liM

Description

The invention relates to instrumentation, in particular to a technique of digital magnetic recording, and can be used in embedded means of operational control of multichannel magnetic recording equipment to ensure control of the accuracy of the recording channels both in the function control mode and during information recording. The purpose of the invention is to increase the accuracy of control recording channels due to the mutual synchronization of input and recording information. Figure 1 shows the functional diagram of the device; FIG. 2 shows timing diagrams illustrating the principle of its operation. A device for monitoring recording channels of a magnetic recording device contains in each of the recording channels an input bus 1 of the recorded digital information, a Z encoding unit, a magnetic head 3, each channel is associated with a synchronization bus 4 of the recorded information and with a synchronization unit 5. In addition, the device contains the first and second switches 6 and 7, block 8, the reference coding block 9, the element NOT 10, and the second registers P and 12, the first and second adders 13 and 14 modulo two, the third adder 15 modulo two and element 16. The device also contains a pulse counter 17 and an output bus 18. The input buses 1 of the recorded digital information are connected to the information inputs of the coding units 2 and to the inputs of the switch 6. The synchronization bus 4 of the recorded information is connected to the inputs of the first clock signal of the blocks 2 coding, with input the house of the synchronization unit 5 with the input of the first sync signal of the reference coding unit 9. The output of the switch 6 is connected to the information input of the ET encoding unit 9. The output of the synchronization unit 5 is connected to the inputs of the second synchronization signal of the coding units 2 and to the input element HE 10, to the input of the second sync signal of the reference coding unit 9 and to the input element AND 16, the output of the HE element 10 is connected to the clock input of the two-digit register 11 and with a clocking input of the two-bit register 12, the outputs of the block 72 72 coding are connected to the inputs of the switch 7 and the inputs of the recording magnetic heads 3. The output of the switch 7 is connected to the information input of the register 1I, the outputs of the first and second bits Secondly, they are connected to the inputs of the adder 13 modulo 2. The output of the reference coding unit 9 is connected to the output bus 18 and to the information input of the register 12, the outputs of the first and second bits of which are connected to the inputs of the adder 14 modulo two. The outputs of the adders I3 and I4 modulo two are connected to the inputs of the adder 15 by the motor two, the output of which is connected to the stroke of the element 16, the output of which is connected to the input of the counter 17 pulses. The specific execution of individual evils and blocks is as follows. The coding blocks 2 and synchronization 5 form, together with the magnetic heads 3, a system of parallel magnetic recording of digital signals with: high density. Reference unit 9 encoding ideitic information blocks 2 encoding. Each coding unit 2 and 9 consists of a cyclic control code generation circuit, a marker introduction circuit (to skew and single-valued decoding during reproduction), a digital information conversion (channel coding) circuit (together with a cyclic control code remainder) in a group coding method, which converts every four input characters to five output characters so that the output information flow contains no more than two further consecutive characters O, and output counting tons a rigger that converts the absolute waveform of the recording (symbol 1 corresponds to a high signal level, symbol O low signal level) to a relative potential form in which each differential corresponds to symbol 1, Synchronization Unit 5 is based on the well-known phase-locked loop and provides clock sync recording with a frequency of about 1.44 times the frequency of the input clock signal of the recorded information. Switches b and 7 are two biscuits of one switch, having a number of positions equal to the number of controlled channels.

The device is designed to control a wide class of modern channels of digital magnetic recording, containing at the output of an encoder a converter of an absolute waveform of a write to a relative one based on a counting trigger.

The device works as follows.

The recorded information in the parallel code is fed to the input bus 1 and is fed to the inputs of the coding units 2 and to the inputs of the switch 6

The accompanying information in the parallel code clock signal is fed to the input bus 4 and then fed to the inputs of the first input clock clock of the coding units 2 for inputting information into them, to the input of the synchronization unit 5 to perform its phase and frequency synchronization with the input clock signal and to the clock clock input coding reference block 9 for inputting input information of one of the channels selected by the switches

The synchronization unit 5 generates a clock sync signal (chart in FIG. 2), the frequency of which is higher than the frequency of the input clock signal, 1.4 times to ensure that the marker symbols are entered into the input information, the remainder of the cyclic control code and the group coding operation.

At the output of coding blocks 2 and 9, there is a counting trigger that converts the output result of the operation of the group coding scheme from absolute to relative form.

The counting trigger is at the output of almost all modern coding schemes (Miller coders), the whole class of group coding coders, the three-period modulation coder.

The principle of control in the proposed device consists in comparing the monitored output signal, i.e. selected by the synchronously operating switches 6 and 7, with the output signal of the reference coding unit 9, the input of which at this time is supplied with the same information signal as that which enters the input of the monitored channel.

The presence of a counting trigger at the outputs of coding blocks 2 and 9 leads to the fact that the output signal of the monitored block 2 (diagrams-i 2 in Fig. 2) and the output signal of the reference block 9 (diagram 3 in Fig. 2) and the output signal of the reference O block 9 (diagram 3 in figure 2) are identical in information content, may have a different initial phase, i.e. they can be randomly either in the phase or in the opposite phase.

Since the comparison can be made only from phased signals, in the proposed device

using two-bit registers 0 and 12 and adders 13 and 14 modulo two, the output signals of the controlled 2 and reference 9 coding blocks are phased. The information shift in registers 11 and 12 is performed using an inverted write clock signal, i.e. the output signal of the element 10, shown in chart 4 (figure 2).

0 The information signal at the output of the first bit and the information signal at the output of the second bit of register 1 are shown in diagrams 5 and 6 (FIG. 2), and the reference signal at the output of the first bit and the reference signal at the output of the second bit of register 12 - on diagrams 8 and 9 (figure 2), respectively.

As a result, at the output of the adder 0 13 modulo two (diagram 7 in figure 2) and at the output of the adder 14 modulo two (diagram 10 in figure 2), the signals are formed in absolute form, corresponding to the BVN code. 5 Comparison of the output signals of the adders 13 and 14 modulo two is carried out by the adder 15 modulo two, the output of which generates a signal (diagram 11 in Fig. 2) in the form of a high level in cases where the value of this clock position of the output signal (eighth the position with symbol 1 in diagram 2, fig. 2) of monitored block 2 of coding 5 differs from the value of the output signal of reference block 9 of coding.

Claims (1)

The modulo two output signal of the adder 15 is gated with a clock 5 clock signal on the AND element 16, the output of which (diagram 12, figure 2) thus produces error pulses, then read by the pulse counter 1 7. In order to control the information channels with the help of the coding reference block 9, it is necessary to be sure of its operability. The verification of the reference coding unit 9 is performed by sending to its input (through one of the input buses 1 and switch 6) a test signal in the form of a pseudo-random sequence of pulses (and the corresponding clock signal on the bus 4) and connecting to the output bus 18 error meter, The well-known principle of action is based on checking the output pseudo-random sequence of block 9 for the rule of its code formation. This check is carried out promptly, since the magnetic recording equipment has recently had a functional control check, when a control test signal is supplied to the inputs of the recording channels, and is equipped with a corresponding error meter. Introduction to the built-in controls of a relatively complex node, which is the reference coding block 9, is economically viable for a multichannel digital magnetic recording system. An apparatus for monitoring recording channels of a magnetic recording apparatus with serially connected magnetic heads and information coding blocks in each of the recording channels, connected by inputs to input buses and inputs of the first switch, a second switch connected by inputs to outputs of information encoding blocks, a control unit connected by inputs to the outputs of the first and second switches and an output to the input of a pulse counter, and a synchronization unit connected by the input to the synchronization bus with one synchronization inputs of the coding and control blocks and an output — with other synchronization inputs of the coding and control blocks, so that, in order to improve the accuracy of control of the recording channels due to the mutual synchronization of the input and recorded information, the control unit contains a reference coding unit, serially connected first register and a modulo two adder, serially connected second register and a modulo-two adder, third modulo-two adder, connected by inputs to the outputs of ne modulo two, the I element connected by one input to the output of the third modulo two adder and the output to the output of the control unit, and the element NOT connected by the output to interconnected synchronization inputs of the first and second registers and the input to the connected between the output of the synchronization unit, another input of the And element and one synchronization input of the reference coding block connected by another synchronization input to the synchronization board, the input to the output of the first switch and the output to the input torogo register, the first register input is coupled with the output of the second switch. JiJiJiJiJTrm 11 1 about about TJlJlJlJlJTm TTL-P. MLJULJUL FIG. 2