SU1003127A1 - Television signal receiving device - Google Patents

Description

(5) DEVICE FOR PRESD TELESIGNALS

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The invention relates to automation and telemechanics, and in particular, can be used in the decoders of the tele-alarm signals of the dispatching equipment of the radio control installed on geographically dispersed radio communication objects.

A device for receiving telemechanical information is known, comprising a drive, logic AND, OR, memory trigger and decoder P.

This device has low noise immunity when operating under the conditions of sequential reception of remote signaling information from geographically dispersed radio equipment due to false phasing of the receiving device, which is formed of information code combinations of the frame combination phased from its correct position.

Closest to the proposed technical entity is a device for decoding cyclic codes, which contains a block of phasing according to the cycle, the input of which is connected to the input of the device and the first input of the first element And, the first output of which is connected to the first inputs of the accumulator and timing distributor, and the second output - with the first

10 input of the clock distributor, and the second output - with the first input of the distributor of elementary pulses, the first output of which is connected to the second input of the first element I, and the second output - to the first input of the code analyzer output, to the second input of which the output of the code analyzer is connected the input of which is connected to the first output of the accumulator tel, and to the second output - the first input of the block of elements I, to the second input of which the second output of the storage device is connected, the third output of which is 31 pdro via the decoder of the key combinations connected to the first the input of the second element is And, the second input of which is connected to the trigger output, and the output is the first input of the trigger and the second input of the clock distributor whose output is connected to the third input of the converter of the code check results, the first output of which is connected to the third input of the AND block whose output forms the output of the device, the output of the first element And is connected to the second output of the accumulator, the second input of the trigger is connected to the output of the converter of the results of the verification of the code containing the two-element OR, the inputs of which are fed respectively, the unit and zero buses of the clock distributor, the outputs of the elements OR are connected to the first Inputs of the elements AND to the second inputs of which the output of the distributor of elementary pulses is connected, and to the third inputs are connected to the outputs of the estimated trigger, to the counting inputs of which the output of the element I is connected, to the input of which is connected the output of the detection unit on the side connected to the drive; The output of the elementary pulse distributor is connected to the second input of the counting trigger, and the outputs of the two elements AND the code check result converter are connected to the inputs of the OR elements, the output of which is connected to the first trigger input, to the second input of which the clock distributor output is connected, to the first and second outputs the trigger includes two elements And, to the second inputs of which the output of the distributor of elementary pulses is connected, and to the third inputs - the output of the clock distributor, the output of the first element And is connected to the input For the block of elements And, the output of the second element And is connected to the reversible counter, the outputs of which through the elements OR are connected to the block of the element C 2 The disadvantage of this device is the low reliability. The reason for the low reliability of the device is the indefinite state of the reversible counter at the time of re-phasing of the device, which leads to the need to delay the analysis of error signals and, consequently, a delay of 7 times to prevent re-phasing over the cycle. This, in turn, leads to the fact that at the moment of following the correct zic-phasing combination the output of the decoder is buried and the phasing is not performed. This is repeated in the next cycle. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that in a device for receiving a television, containing a phasing unit, the input of which is combined with the first input of the first element I and connected to the input of the device, the first output of the phasing unit is connected to the first input of the accumulator and the first input of the first pulse distributor, the second and third outputs of which are connected respectively to the first, second and third inputs of the code converter, the first output of which is connected to the first input of the AND block, the second output of the phasing block It is connected to the input of the second pulse distributor, the first and second outputs of which are connected respectively to the fourth input of the code converter and the second input of the first element I, the output of which is connected to the second input of the accumulator, the first output of which through the first decoder is connected to the first input of the second element And the output of the second element And is connected to the second Input of the first pulse distributor and the first input to the trigger, the output of which is connected to the second input of the second element And, the second and third outputs of the storage device are connected to p By the second and second inputs of the code analyzer, the first and second outputs of which are connected respectively to the fifth input of the code converter and the second input of the AND block, the third input of which is connected to the fourth output of the accumulator, and the output to the output of the device, the second decoder and shift register are entered, the second output of the code converter is connected through the serially connected shift register and the second decoder is connected to the second trigger input. In addition, the code converter is made on AND, OR, NOT and trigger elements, the outputs of the first and second elements OR are connected to the first inputs of the first and second elements respectively

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And, the outputs of which through the third element OR are connected to the first input of the trigger, the outputs of the trigger are connected to the first inputs of the third and fourth elements AND, the second input of the first element AND through the element is NOT connected to the second input of the second element And, the second input of the trigger, the inputs of the first and second the OR elements, the combined second inputs and the combined third inputs of the third and fourth elements AND and the second input of the second element AND are connected respectively to the first - the fifth inputs of the code converter, the outputs of the fourth and third elements ntov And connected to the first and second outputs of the code converter, respectively. In addition, the code analyzer is made on series-connected modulo-two adders, the output of the latter of which is connected to the first output of the code analyzer, the second input of each modulo-two adder is connected to the corresponding first input of the code analyzer, the second input and the output of which are connected to the first input of the first modulo two.

FIG. 1 shows a block diagram of the device; in fig. 2 - execution of the code converter; in fig. 3 execution of the code analyzer; in fig. k - time diagram of the device.

A device for receiving television signals (Fig. 1) contains a block of 1 phasing according to a clock, a distributor 2 clocks, an element 3, a decoder k of a code combination phasing a cycle, a trigger 5, an element 6, a drive 7 a distributor 8 clocks, a converter 9 of a code , code analyzer 10, block 11 elements And, decoder 12, shift register 13.

Converter code 9 contains (Fig. 2) the elements OR, the elements And 17-20, the element is NOT 21 and the trigger 22.

The code analyzer 10 (FIG. 3) is 11, not on the adders 23 modulo two.

The device receives remote signaling signals from groups of geographically dispersed radio facilities.

The device operates as follows.

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Channels are sequentially connected to the input of the device, through which tele-signaling data on the state of radio equipment located at geographically dispersed radio communication objects is transmitted cyclically in a continuous sequence.

The telealarm data in the form of a sequence of cyclic phasing code combinations is fed to the input of the device, as well as to the inputs of the first element And 6, the phasing unit 1 in cycle P. After the And 6 element is sampled, the signaling code combinations (cycle phasing and informational code combinations) are entered and are recorded in the accumulator 7. At the same time, the sending of the code combinations of the signaling system is fed to the input of the phasing unit 1 according to the clock, the clock pulses from the output go to the distributor 2, in the input d accumulator 7 and the input of the distributor 8. The pulses at the output of the distributor 8 are distributed over the stroke h serve to synchronize the operation of the device for its elements. One of the pulses, which exactly coincides with the middle of the stroke, is fed from the distributor 8 to the input of the element 6 and serves to strobe the incoming information to the device.

After decryption by the decoder C, through element I 3, a reset pulse is applied to the input of the distributor 2. Simultaneously trigger. 5 tilts and prohibits re-decryption of cyclic phasing code combinations. As you enter into drive 7, code combinations are checked for cooTBeTCt due to the encoding law by analyzer 10.

The code analyzer 10 is designed to check the code for compliance with the coding law on the check polynomial.

The analyzer consists of modulators 23 modulo two interconnected with memory elements of accumulator 7. Analyzer 10 output is the output of the last one from the chain of adders 23, while the outputs of the remaining adders 23 of the chain are connected to the inputs of subsequent adders 23 of the chain.

The number of adders 23 in the analyzer 10 is equal to the number of non-zero 7.10 coefficients of the test polynomial without one. The check polynomial Q (X) is formed by dividing the polynomial X +1 by the generating polynomial of the code P (X) used in the tele-alarm system. The degree of Q (X) is equal to the number of check bits of the M code, N is the total number of code bits. The operation of the analyzer 10 is as follows. The remote signaling information is output from output 6 and is recorded in storage device 7. As it is recorded and advanced from the outputs of memory elements of storage device 7, corresponding to non-zero coefficients of the test polynomial, signals are sent to the first inputs of modulators 23 modulo two. The second inputs of the adders 23 of the analyzer 10. The signals from the outputs of the previous adders 23 of the analyzer 10 are fed. Two inputs of the first adder 23 are fed from the outputs of two memory elements of the accumulator 7. The output of the first adder .23 produces a signal corresponding to one if there is an odd number units and g zero for an even number of units. Thus, in the presence of an even number of units on the analyzer input, a zero signal is formed at the output, and in the presence of an odd number, a single signal is produced. The results of the verification of code combinations are transformed by the code converter 9, which is intended to maintain the results. Check any adjacent code into a form that should be obtained when checking any ordinary code. If the code verification procedure for; Compliance with the coding law (modulo two a) using a test polynomial can be written R (X) S (X) .Q (X), where S (X) is a code combination polynomial; C1 (X) is the check polynomial of the code, then the procedure of the converter of the results of the verification of the code can be represented as modulo two polynomials of the test result R (X) with the transforming polynomial H (X). The transforming polynomial must satisfy condition H (X) ®R (X) O Converter 9 works as follows. 7 From the output of the distributor 2, single clock pulses go to the inputs of the first element OR k, zero clock pulses go to the inputs of the second element OR 15 At the output of the first element OR 14 a sequence of pulses is formed corresponding to a single clock pulse (for example, 0.1001), and at the output of the second element OR 15 - zero (for example 10110). These pulse sequences are received, respectively, at the first inputs of the first and second elements AND 17 and 18. At the second input of the second element And 18, a code combination arrives corresponding to the result of checking the adjacent class of the code R (X) (for example, 01001), and at the second input of the first element AND 17 comes the same combination, but in an inverted form (e.g. 10110). In the event that the received code combination does not contain distortions at the output of the analyzer 10 of the code, the combination corresponding to the full H (X) will be determined. The addition of R (X) with zero clock pulses and an inverted R (X) value with unit clock pulses give a zero result. If there is a distorted code combination of remote signaling received at the input of the device, the result of checking for compliance with the coding law is not equal to H (X), and the output of either the first or second element I 18 is generated by impulses - signals of distortion detection. At the beginning of the test, the first input of the trigger 22 is given a reset pulse to the initial state from the output of the distributor 2. After checking the code combination, if there is no distortion, the trigger 22 remains in the initial state, and if there are distortions, one of the checks is tilted. As a result of checking the next code combination recorded in device accumulator 7, from the first output of trigger 22 an element 19 records a pulse to the input of the shift register 13, and from the second output of the trigger 22 through element 20 a pulse is fed to the input of the 11 elements I. there is no distortion in the received code combination, then from the second output of trigger 22 a pulse arrives through element 1 20 allowing reading through block 11 recorded in the accumulator 7 of the code combination; from the first output of the trigger 22 through the element And 19 to the input of the register 13 sd g pulse does not arrive, but at the end of the test code combination, register 13 takes a step and it is the first one. the memory location is zero. In the absence of distortion, register 13 is zeroed. If in the received code combination the distortions are detected, then from the first output of the trigger 22 through the element 19 the pulse 13 enters the input of the register 13. From the second exit three hera 22 through the element I 20 on. the input of block 11 does not give a pulse, therefore there is no permission to read the information. Thus, the code converter 9 converts the results of the verification of the code combination television signaling transmitted by any adjacent classes of codes, and the form that can be obtained by checking the ordinary code. In the process of receiving the TV signaling information, a cycle pattern phasing code pattern can be formed from the part of the previous one and part of the following code combinations. If this code combination is recorded in accumulate 7 after the device has been phased and its cycle and cycle, then the signal to it from the output of the decoder k does not reach the clock allocator, so. as after the establishment of the correct cyclic phase, the level of interference in the channel is small, the frequency of detection of distortions corresponds to their frequency: - formation, trigger 5 is in the state of no re-phasing. If a false cyclic phase is registered before the arrival of a true cyclic phase code pattern, it shifts and the frequency of generation of distorted code patterns sharply increases, since the correspondence to the coding law is broken. The operation of the device in this mode is shown in FIG. k, where o is the signal from the output of the decoder; 5 - state of register .13 shift; B - the moments of the formation of the error signal (CO); about. 710 timing diagram for the encoder to transmit the signal (AL) data of the remote signalization and reception data with the help of a receiver (PU) of this data. Since the cyclic phasing code combination is included in the telealignment cycle. Since, after a false cyclic phase has been established, the probability of distortion of the code combinations increases to 0.95-0.99 (L.9), the shift register 13 constantly has from (L-1) to L detection signals written in the register as units. Therefore, after false phasing, almost immediately after receiving the first code combination, the cyclic phasing prohibition release signal is generated, which from the output of the decoder 12 enters the second input of the trigger 5. The phasing prohibition time (Fig.) Is sharply reduced to one code combination, and a continuously incoming stream The code pattern distortion detection signals generated by the decoder 12 when the operation threshold S is exceeded continuously support the trigger 5 in the phase permitting state. A true cyclic phasing code combination can ensure that the correct cyclic phase is set even if it follows immediately after a false combination. After the correct cyclic phase has been established, the frequency of the formation of an error is reduced to, which leads to a quick (during reception of 2-3 code combinations) release of the shift register 13 and its lower state below the threshold. After the correct cyclic phase has been established, the rephasing resolution signal is no longer generated, since, despite the shift register state above S, the distortion detection signal is not received. Since the shift register 13 is in the state above the threshold after false phasing, the reception of the next code combination leads to the formation of the enable signal of the second phase phasing, which creates conditions for the rephasing to occur immediately after the south. In this connection, the operation of the device under the conditions of successive reception of tele-signaling signals from groups of geographically dispersed radio equipment is performed more reliably.

The technical and economic efficiency of the proposed device consists in increasing the reliability of data acquisition from the remote signaling of geographically dispersed radio equipment. I

Claims (3)

Invention Formula A device for receiving television signals containing a phasing unit, the input of which is combined with the first input of the first element I and connected to the input of the device, the first output of the phasing unit is connected to the first input of the accumulator and the first input of the first pulse distributor, the first, second and third outputs of which are connected respectively with the first, second and third inputs of the code converter, the first output of which is connected to the first input of the block of elements And, the second output of the block of phasing is connected to the input of the second distributor pulses, the first and second outputs of which are connected respectively to the fourth input of the code converter and the second input of the first element I, the output of which is connected to the second input of the accumulator, the first of which is connected to the first input of the second element I through the first decoder, the output of the second element I is connected to the second input the first pulse distributor and the first input of the trigger, the output of which is connected to the second input of the second element I, the second and third outputs of the accumulator are connected to the first and second inputs of the code analyzer, The first and second outputs of which are connected respectively to the fifth input of the code converter and the second input of the block of elements I, the third input of which is connected to the fourth output of the accumulator, and the output to the output of the device, so that in order to increase the reliability of the device, the second decoder and shift register are entered into it, the second output of the code converter is connected through the serially connected shift register and the second decoder is connected to the second trigger input. 2. The device according to claim 1, which means that the code converter is executed on the elements AND, OR, NOT and trigger, the outputs of the first and second elements OR are connected to the first inputs of the first and second elements respectively, the outputs of which through the third element OR are connected to the first input of the trigger, the outputs of the trigger are connected to the first inputs of the third and fourth elements And, the second input of the first element AND through the element is NOT connected to the second input of the second element AND, the second input of the trigger, the inputs of the first and second elements OR, the combined second inputs and the combined third inputs of the third and fourth elements And the second input of the second element And are connected respectively to the first - the fifth inputs Q converter code, the outputs of the fourth and third elements And connected to the first and second outputs of the code converter, respectively. 3. The device according to claim 1, that is, that the code analyzer is made on serially connected modulo-two adders, the output of the last of which is connected to the first output of the code analyzer, the second input of each modulo-two adder is connected to the corresponding first input code analyzer, the second input and output of which. go connected to the first input of the first adder modulo two. Sources of information taken into account in the examination 1. USSR author's certificate number 809300, cl. G 08 C 19/28, 1979. 2. USSR author's certificate №, cl. H L 3/02, 1975 (prototype). tJi ( / Lja fj5f / g. /  f eight lAr- c / 7 - of L fff fff "-J g ht - rj .  five