JPH0738626B2 - Word sync detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a word synchronization detection circuit for digital communication. In particular, it relates to a word detection circuit using a syndrome obtained as a result of an error detection calculation.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of an error correction encoder on the transmission side of a digital communication system. FIG. 3 is a block diagram of a conventional word synchronization detection circuit.

Conventionally, as shown in FIGS. 2 and 3, a word synchronization detection circuit inputs an error-correction-coded coded data signal 102 from an error-correction encoder 1 on the transmission side to detect an error. It is composed of an error correction arithmetic unit 6 which performs synchronization determination and error correction using the error detection result and outputs a corrected data signal.

Next, the operation will be described. In the error correction calculator 6, an error detection calculation is performed on the encoded data signal 102 that is an input. If the syndrome obtained as a result of the error detection operation indicates that there is an error, the coded data signal 102 is shifted by 1 bit and the error detection operation is performed again, and the 1-bit shift operation and the error detection are performed until the syndrome indicates that there is no error. Calculation continues. If the syndrome indicates that there is no error, the 1-bit shift operation is stopped, the error detection operation is further continued, and if the syndrome indicates that there is no error for consecutive M (M: an integer of 2 or more) times, it is regarded as synchronous and the error correction operation is performed. Corrected data signal 10 after being broken
3 is output.

As a related technique, there is one disclosed in Japanese Patent Laid-Open No. 64-68038.

[0006]

However, in such a conventional word synchronization detection circuit, the maximum number of shifts required for synchronization detection is the number of bits included in one block (block: code length used for error correction operation). However, there is a drawback that the synchronization determination time becomes long because it is only necessary.

The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a word synchronization detection circuit which can shorten the synchronization determination time.

[0008]

SUMMARY OF THE INVENTION According to the present invention, word synchronization detection is provided with error correction calculation means for inputting a coded data signal transmitted from a transmission side and subjected to error correction coding as one word and performing error correction decoding. In the circuit, the encoded data signal is converted from 1 bit to (n-1) bits (n is 2≤n≤).
(N-1) delay elements for delaying each of the (n-1) delay-encoded data signals and outputting the (n-1) delay-encoded data signals and the (n-1) delayed coded data signals. A timing generator that generates a timing signal indicating the start point of the error detection calculation for each of the delay-coded data signals, and the error calculation means is based on the timing signal from the timing generator. And (n-1) delay-encoded data signals, including n error-correction calculators for performing error-detection calculations and synchronization judgments and outputting synchronization judgment signals, respectively. And a sync data signal selector for selectively outputting the sync data signal according to a sync determination signal from the device.

In the present invention, the coded data signal may include a check bit for each word, and the error correction calculator may include a means for calculating a syndrome using the check bit.

Further, according to the present invention, the error correction calculator may include means for outputting a correction data signal together with the synchronization determination signal when synchronization is established.

In the present invention, the timing generator may include means for outputting the timing signal based on the block pulse from the n error correction calculators.

[0012]

The maximum number of hunting times is 1 / n as compared with the case where there is only one error correction arithmetic unit by having n error correction arithmetic units on the receiving side and performing n kinds of synchronization determination processing simultaneously in parallel. Therefore, the synchronization determination time can be shortened. The above-mentioned Japanese Patent Laid-Open No. 64-68038 discloses a technique for promptly synchronizing by detecting a plurality of different phases for frame synchronization. However, the present invention is word synchronization, and within the word Differs in that it does not have a synchronization identification signal for detecting synchronization and that synchronization is established by an error correction calculation.

[0013]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a word synchronization detection circuit according to an embodiment of the present invention. In FIG. 1, the word synchronism detection circuit is provided with an error correction calculation means for inputting the encoded data signal 102 transmitted from the transmission side and subjected to error correction encoding as one word and performing error correction decoding.

A feature of the present invention is that the encoded data signal 102 is delayed from 1 bit to (n-1) bits (n is 2≤n≤error correction code length) (n-1). ) Delay-decoded data signals 104 _{1 to} 104
(n-1) delay units 4 ₁ to 4 _n-1 which output _n-1 ,
A timing generator 5 that generates a timing signal indicating the start point of the error detection calculation for the encoded data signal 102 and the (n-1) delayed encoded data signals 104 _{1 to} 104 _n-1 . It said error calculating means, calculating a respective error detection on the encoded data signal 102 and (n-1) number of delay encoded data signal 104 ₁ ~104 _n-1 based on the timing signal 108 from the timing generator 5 And the synchronization determination is performed and the synchronization determination signal 106 ₁
Includes n error correction calculator 2 ₁ to 2 _n to output - 106 _n-1, respectively, selectively outputs the synchronized data signal 109 by the n synchronization determination signal from the error correction calculator 2 ₁ to 2 _n This is because the synchronous data signal selector 3 is provided.

Further, the encoded data signal 102 includes check bits in word units, and the error correction arithmetic units 2 ₁ to 2 _{n are included.}
Includes means for calculating the syndrome using this check bit.

Further, the error correction calculators 2 ₁ to 2 _n include means for outputting the correction data signals 105 _{1 to} 105 _n-1 together with the synchronization determination signals 106 _{1 to} 106 _n-1 when the synchronization is established.

Further, according to the present invention, the timing generator 5 has n
Block pulse 1 from each of the error correction calculators 2 ₁ to 2 _n
A means for outputting the timing signal 108 based on 07 _{1 to} 107 _n is included.

The operation of the word sync detection circuit having such a configuration will be described.

On the receiving side, the coded data signal 102 and the 1-bit delay coded data signal 104 ₁ , ..., The n-1 bit delay coded data signal 104 _n-1 correspond to the error correction calculator 2 ₁ and the error correction unit, respectively. calculator 2 _2, ..., are input to the error correction calculator 2 _n.

The timing generator 5 generates a timing signal 108 based on the block pulse 107 ₁ , block pulse 107 ₂ , ..., Block pulse 107 _n output from the n error correction calculators.

In the error correction calculator 2 ₁ , the error correction calculator 2 ₂ , ..., The error correction calculator 2 _n , the timing signal 10
8, an error selection calculation is performed in synchronization with each other, and if the syndromes that are the calculation results in all the error correction calculators indicate that there is an error, the encoding that is the input of each of the error correction calculators 2 ₁ to 2 _n The data signal 102, the _1- bit delay coded data signal 104 ₁ , ..., The n-1 bit delay coded data signal 104 _n-1 are each shifted by n bits and an error detection operation is performed.

In this way, the n-bit shift and the error detection operation are repeated until the syndrome indicates that there is no error in any of the error correction arithmetic units 2 ₁ to 2 _n . If the syndrome indicates that there is no error in the error correction calculator 2 _k (k: a natural number of 1 or more and n or less), the error correction calculator 2 stops the n-bit shift and continues the error detection calculation, and M (M: 2 or more) If the syndrome shows no error for consecutive (integer) times, it is considered as synchronization. The correction data signal 105 ₁ , the correction data signal 105 ₂ , ..., The correction data signal 105 _n and the synchronization determination signal 106 ₁ , the synchronization determination signal 106 ₂ , ..., The synchronization determination signal 106 _n are input to the synchronization data signal selector 3. And based on the synchronization determination signal,
The synchronous data signal 109 is selectively output.

As described above, the n number of error correction arithmetic units perform the synchronous determination in parallel at the same time, so that the maximum required number of n-bit shifts is 1 / n of the case where there is one error correction arithmetic unit. Can be shortened.

[0025]

As described above, the present invention has an excellent effect that the synchronization determination time can be shortened.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a word synchronization detection circuit according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of an error correction encoder on the transmission side of a digital communication system.

FIG. 3 is a block configuration diagram of a conventional word synchronization detection circuit.

[Explanation of symbols]

1 Error Correction Encoder 2 ₁ to 2 _n Error Correction Calculator 3 Synchronous Data Signal Selector 4 ₁ 1 Bit Delay 4 _n-1 (n-1) Bit Delay 5 Timing Generator 6 Error Correction Calculator 101 Transmission Data signal 102 Encoded data signal 103, 106 _{1 to} 106 _n Corrected data signal 104 ₁ 1-bit delayed encoded data signal 104 _n-1 (n-1) bit delayed encoded data signal 105 _{1 to} 105 _n Corrected data signal 106 _{1 to} 106 _n sync determination signal 107 _{1 to} 107 _n block pulse 108 timing signal 109 sync data signal

Claims (4)

[Claims] 1. A word synchronism detection circuit comprising error correction calculation means for inputting, as one word, a coded data signal transmitted from a transmission side and subjected to error correction coding as error correction decoding. From 1 bit to (n-1) bits (n is 2≤n≤error correction code length), and outputs (n-1) delayed encoded data signals (n-
1) number of delay devices, and a timing generator that generates a timing signal indicating a start point of an error detection calculation for the coded data signal and the (n-1) number of delayed coded data signals The error calculating means is configured to transmit the coded data signal and (n- based on the timing signal from the timing generator.
1) n error correction calculators for performing error detection calculation and synchronization judgment for each of the delay coded data signals and outputting synchronization judgment signals respectively, and synchronization from the n error correction calculators is included. A word sync detection circuit comprising a sync data signal selector for selectively outputting a sync data signal according to a determination signal. 2. The word synchronization detection circuit according to claim 1, wherein the coded data signal includes a check bit in units of words, and the error correction arithmetic unit includes means for calculating a syndrome using the check bit. 3. The word synchronism detection circuit according to claim 1, wherein the error correction calculator includes means for outputting a correction data signal when synchronism is established together with the synchronism determination signal. 4. The word synchronization detection circuit according to claim 1, wherein said timing generator includes means for outputting said timing signal based on block pulses from said n error correction arithmetic units.