JPH01160232A - Correlation detecting circuit - Google Patents

Abstract

PURPOSE:To facilitate the executions of an integrated circuit and a low energy consumption by outputting a pattern correlation detecting pulse when the number of adding bits outputted from an adding means to add the number of coincidence/non- coincidence bits and the number of inverse adding bits outputted from an adding value inverting means for within the ranges of the permissible number of errors, respectively. CONSTITUTION:By a comparing part 7, whether an addition result supplied from an adding part 4 is within the range of the permissible number of error bits corresponding to a correlation value set to a permissible value setting part 6 or not is compared. When the number is within the range, that a pattern set beforehand is correlation- detected is considered, and a correlation detecting pulse DET is outputted. By an inverting part 5, the addition result added by the adding part 4 is inverted for each bit. A comparing part 9 compares an inversion result B which is the output of the inverting part 5 with a permissible number of errors EB, and when the B is within the range of the EB, that the correlation detection is executed to an inverting pattern is considered, and a correlation detecting pulse INV DET is outputted. Consequently, for the adding part 4, one part is sufficient, and moreover, the constitution of the pattern inverting part 5 can be made small.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-to-phase detection circuit that detects the correlation between a digital signal transmitted in a digital signal transmission system and a predetermined pattern, and particularly relates to the circuit configuration thereof. The present invention relates to a phase-to-phase detection circuit that can be easily integrated into a circuit and reduce power consumption by downsizing the circuit.

[Prior Art] In a digital signal transmission system, for example, when transmitting multiplexed data, a time reference may be required to distinguish which part of transmitted data corresponds to what data. For this reason, in general, a synchronization signal or the like is specially inserted as a specific pattern different from other data.

Then, on the receiving side, by receiving this specific pattern, it is recognized as detection of a synchronization signal, and this is used as a time reference for reception timing. That is, in accordance with this time standard, the received data is separated or demodulated, or the beginning of the received data or its presence or absence is detected, and the original digital signal is reproduced or extracted or the same group is established.

In such a method, it is essential to detect a synchronization signal that is a specific pattern. Detection of this synchronization signal is basically performed as follows. First, a synchronization signal pattern having a predetermined unique pattern is prepared as a reference pattern for comparison. Then, this reference pattern for comparison is compared with the data pattern in the received data, and a mismatch or coincidence is determined for each corresponding bit.

However, in a wireless transmission path, errors may occur in data. For this reason, a correlation detection method that allows a certain degree of bit error is adopted to detect the synchronization signal.

Here, this number of bit errors allowed to a certain extent is called the number of allowable errors.

FIG. 2 is a block diagram of a conventional correlation detection circuit.

In the figure, l is a serial/parallel converter that converts input data DATA from serial data to parallel data, and 2.12 is an exclusive OR circuit, which compares the set pattern and parallel data. 3 is a pattern setting unit that sets a pattern for detecting correlation; 4, 14
is an adder that adds the number of mismatched bits that is the output of the pattern comparison unit 3; 6 and 16 are tolerance setting units that set the number of tolerance errors corresponding to the correlation value; and 7 and 17 are tolerance value setting units for each input. If the number of errors is within the range, the correlation detection pulse DE
A comparator unit that outputs T or INV DET, and lO an inverter that inverts each bit of the set pattern.

In addition, DATA is input data, DET is correlation detection output,
INV DET indicates the correlation detection output for the inversion pattern, respectively.

In the above configuration, the received data is input to the serial/parallel converter l as input data DATA, and is sequentially converted from serial data to parallel data. This serial-to-parallel converter 1 can be configured with, for example, a shift register. next,
This parallel data and the reference pattern data set by the pattern setting section 3 are input to the pattern comparison section 2, and each bit is compared. Also, at this time, the pattern reversing section 10 prepares an inverted version of the reference pattern data set by the pattern setting section 3.

Then, this inverted pattern and the above-mentioned parallel data are input to the pattern comparing section 12, and a comparison is also performed for each bit.

The comparison result for each bit is input to each adder 4.14. This adder 4 adds the mismatching bits that are the comparison results in the pattern comparing section 2, and calculates the total. Then, the total result of the number of mismatched bits is output to the comparator 7. The comparison unit 7 compares the total number of mismatched bits with the number of allowable errors corresponding to the correlation value set by the allowable value setting unit 6. If the number of errors is within the allowable number of errors, a correlation detection pulse DET is output, assuming that the synchronization signal, which is a reference pattern, has been correlated.

On the other hand, correlation detection for inverted patterns is similarly performed. That is, the pattern comparing section 12 compares the parallel pattern and the inverted pattern, and the adder 14 adds the mismatched bits as a result of the comparison. Then, the comparison unit 17 compares the output total with the allowable number of errors from the allowable value setting unit 16, and if it is within the range of the allowable error number,
INV as interphase detection pulse for inversion pattern
DET is output.

By the way, in the case of a conventional correlation detection circuit, two pattern comparison sections 2, 12 and two addition sections 4, 14 are used, resulting in a large circuit configuration. Furthermore, the scale of this line increases as the bit length of patterns such as synchronization signals becomes longer.

For example, let's calculate the circuit size assuming a pattern length of 30 bits.

First, when the pattern comparison section 12 is constructed of exclusive OR circuits, 30 of these are required. Next, if the adder 14 is constructed of binary number adder circuits, there will be ten 1-bit full adder circuits and five 2.3-bit and 4.5-bit adder circuits, respectively. 2. 1. One adder circuit is required, and a total of 19 adder circuits are required, including the full adder circuit and the adder circuit. This is because the number of mismatched bits is added in sequence, such as adding the result of a 1-bit full adder circuit in the next adder circuit.

Therefore, the total number of circuits in the pattern comparing section 12 and the adding section 14 is 49, resulting in a large scale and an increase in power consumption.

[Problems to be solved] The conventional correlation detection circuit described above uses two pattern comparison sections and two addition sections, which results in a large circuit configuration and is not suitable for integrated circuits and low power consumption. There was a problem.

The present invention has been made in view of the above problems, and aims to provide a correlation detection circuit that can easily achieve integrated circuit integration and lower power consumption by downsizing and simplifying the circuit configuration.

Solution to Problem E] In order to achieve the above object, the correlation detection circuit of the present invention converts an input digital signal from serial to parallel, and converts a predetermined pattern into a pattern that detects coincidence/mismatch for each bit. a comparison means, an addition means for adding up the number of match/mismatch bits output from the pattern comparison means, an addition value inversion means for inverting the number of bits to be added bit by bit outputted from the addition means, and the above-mentioned addition a first comparing means for outputting a set pattern correlation detection pulse, determining that correlation has been detected when the number of addition bits outputted from the means is within the range of the number of allowable errors; and a second comparing means that outputs an inverted pattern correlation detection pulse, determining that correlation has been detected when the number of addition bits is within the range of the allowable number of errors for inverted patterns.

[Example code] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a phase-to-phase detection circuit according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

In the figure, 5 is an inversion unit that inverts each bit of the addition result that is the output of the addition unit 4, 8 is a tolerance setting unit that sets the number of allowable errors corresponding to the correlation value, and 9 is the output of the inversion unit 5. On the other hand, if it is within the allowable number of errors, the correlation detection pulse INV
This is a comparison section that outputs DET.

In the above configuration, first, the received serial data is sequentially input to the serial/parallel converter l as input data DATA, and is sequentially converted into parallel data. Next, this parallel data is input to the pattern comparison section 2, where it is compared bit by bit with the pattern output from the pattern setting section 3, and the pattern comparison section 2 compares each bit with the pattern outputted from the pattern setting section 3.
Detect discrepancies. The mismatched hits that are the output of the pattern comparison section 2 are supplied to the addition section 4, which adds them together and then distributes them to the comparison section 7 and the inversion section 5.

The comparator 7 compares whether the addition result supplied from the adder 4 is within the range of the allowable number of error bits corresponding to the correlation value set in the allowable value setting unit 6. If it is within this range, it is determined that the correlation of the preset pattern has been detected, and a correlation detection pulse DET is output.

Further, the inverter 5 inverts the addition result added by the adder 4 bit by bit. In the case of binary operations, this means taking the complement.

For example, let A be the addition result of mismatched bits, I be the number of bits of A, B be the inversion result of A, E be the allowable error number for the inversion pattern, and N be the number of bits of the detection pattern (however,
A, B, K, E, and N are integers. )
. Then, the inversion result B is B, = 2 -1 - A...
(1) The inverted pattern is detected when N-A≦E (2) is satisfied.

For example, N=30. When A = 28, detection of an inverted pattern means that 28 bits are inconsistent, or incorrect, with respect to a 30-bit long pattern (non-inverted pattern); This means that 28 bits match. That is, since only 2 bits were incorrect for the inverted pattern, if E is set to 2 or more, equation (2) is satisfied and the inverted pattern is detected between phases.

By the way, if we correct both sides of equation (2) by adding -1-N to 2, satisfying equation (2) means (2ゝ-1-N)+ (N-A) ≦E+ ( 2 -1-N) 2'-1-A≦E+2" 1-N - (3), and if the correction result on the right side is set to EB=E+2-1-N, then from equations (1) and (3) B≦EB, which is equivalent to satisfying this condition.

That is, by setting the allowable error number in the allowable value setting section 8 to EB, which is the correction value 2 plus -1-N, instead of the conventional E, the following results.

The comparison unit 9 compares the inversion result B, which is the output of the inversion unit 5, with the allowable error number EB, and the inversion result B is the allowable error number EB.
If it is within the range (below), it is possible to output the correlation detection pulse INV DET, assuming that the correlation has been detected for the inverted pattern.

With this configuration, not only one addition section 4 is sufficient, but also the configuration of the pattern inversion section 5 can be made smaller.

Here, the pattern reversal unit 10 of the conventional example shown in FIG.
Let's compare the circuit scale of the inversion section 5 shown in the figure.

The pattern inverter IO is a circuit that inverts all bits (n) of the pattern, and the inverter 5 inverts the bits (k) of the binary addition results. For example, if N=30, the addition result is 30 or less even if all bits match or do not match. And 2'
>30, so when configuring the reversing section 5, ■(
= 5 will be sufficient. That is, N>K is always satisfied, and the circuit scale of the inversion section 5 is smaller than that of the pattern inversion section 10.

It should be noted that the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the embodiments described above, the mismatch bits are used for correlation detection, but it is clear that the same result can be achieved even if the match bits are used. However, in that case, the number of bits for comparing the addition results increases, so it is not used much.

[Effects of the Invention] As explained above, the present invention can be configured with one pattern comparison section and one addition section, and the inversion section can also be configured with a smaller circuit scale than the conventional example. This has the advantage that the scale of the entire circuit configuration is significantly reduced, and a correlation detection circuit that can be easily integrated and has low power consumption can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase-to-phase detection circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional correlation detection circuit. l: Serial/parallel conversion section 2: Pattern comparison section 3: Pattern setting section 4: Addition section 5: Inversion section 6.8: Tolerance value setting section 7.9: Comparison section

Claims (1)

[Claims] Pattern comparison means for converting an input digital signal from serial to parallel and detecting a match/mismatch for each bit with a predetermined pattern, and a match/mismatch output from the pattern comparison means. addition means for adding the number of bits;
Addition value inversion means for inverting the number of addition bits outputted from the addition means bit by bit; and a set pattern in which correlation is detected when the number of addition bits outputted from the addition means is within the range of the number of allowable errors. When the number of addition bits of the inversion outputted from the first comparison means for outputting a correlation detection pulse and the addition value inversion means is within the range of the number of allowable errors for inversion patterns, the correlation is determined to have been detected and the inversion pattern correlation is detected. A correlation detection circuit comprising: second comparison means that outputs a pulse. (2) The pattern comparison means includes a serial-to-parallel conversion unit that converts the input digital signal from serial to parallel, a pattern setting unit that sets in advance an arbitrary pattern necessary for detecting correlation, and a pattern setting unit that converts the input digital signal from serial to parallel; The device includes a pattern comparison unit that detects coincidence or mismatch for each bit between the pattern set by the setting unit and the parallel data output from the serial/parallel conversion unit, and the first comparison unit is configured to perform correlation processing. a first tolerance setting section for setting the number of tolerance errors corresponding to the correlation value for detection; the number of tolerance errors output from the first tolerance setting section; and the number of bits to be added output from the adding means. and a comparison unit that outputs a set pattern correlation detection pulse as a correlation detection pulse when the number of addition bits is within the range of the allowable number of errors, and the second comparison means outputs a set pattern correlation detection pulse. a second tolerance setting section for setting the number of tolerable errors for the inversion pattern corresponding to the correlation value for detecting the correlation for the inversion pattern; and a second tolerance setting section for the inversion pattern outputted from the second tolerance setting section. The allowable number of errors is compared with the number of addition bits of the inversion outputted from the addition value inversion means, and if the number of addition bits of the inversion is within the range of the allowable number of errors for the inversion pattern, the correlation is detected and the inversion pattern is processed. 2. The correlation detection circuit according to claim 1, further comprising a second comparison section that outputs a correlation detection pulse.