JPH1028146A - Code error correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a correct system operation by receiving a high-speed clock and a digital signal consisting of plural bits and correcting the error of a logical value over the whole time base area of one bit. SOLUTION: The digital signal of the input of an input terminal 1 is executed over-sampling by the high-speed clock in a transmitting part 3 and inputted to an error detecting part 4 with a transmission path 10 as sample data. The input data includes a logical value error owing to noise, etc. A detecting part 4 takes-out the logical pulse signal A at the time of the optional high-speed clock and the logical pulses B and C at the time of the high-speed clock after and before it, compares the pulse A with B and with C by an EX-OR circuit 42, outputs an error pulse 7 from the circuit 42 at the time of difference in both and transmits the high-speed clock at the optional point of time and a logical pulse signal to an error correcting part 5. The correcting part 5 inverts data when the error pulse 7 exists in the logical pulse signal of the high-speed clock at the optional point of time. Output data of the correcting part 5 is outputted from a terminal 6 as code error correcting data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code error correction device, and more particularly to a code error correction device for correcting a data code having a partial error due to a transmission path or the like.

[0002]

2. Description of the Related Art A conventional code error correction circuit of this type will be described with reference to the drawings.

FIG. 5 is a block diagram showing an example of a conventional code error correction circuit, and FIG. 6 is a diagram for explaining an outline of processing in the conventional example.

FIGS. 5 and 6 show a conventional example disclosed in Japanese Patent Application Laid-Open No. 1-170250. In the case where a start bit is detected by a start bit detection circuit 21 in response to data reception, the start bit detection circuit shown in FIG. The sampling timing circuit 22 outputs a sampling request signal to sample the subsequent data (including the parity bit) eight times in bit units based on the instruction from 21. 8 continuous sampling circuits 2
In No. 3, the vicinity of the center of each data is continuously sampled eight times in synchronization with the clock from the clock generation circuit 24 based on the sampling request signal. Eight sampling data (state data) sequentially obtained for each of the data are stored in a predetermined order in a sampling register 26 and input as an address to an 8 → 1 bit conversion table storage ROM 27 so that 1-bit conversion data (majority decision) is obtained. (The state of the resulting data).

That is, in this conventional example, as shown in FIG. 6, each of bit unit data D _{0 to} D ₆ constituting original received data in an asynchronous serial data format (in this conventional example, start-stop synchronization type) and parity. For the bit, the data state near the center is continuously sampled eight times, and the state of the data is determined by the majority decision of the eight sampled state data. The converted data indicates data as a result of the majority decision. Although the process for only the data D ₀ as shown are illustrated, those which are treated in the same manner for the other data D ₁ to D ₆ and a parity bit.

It is to be noted that only the data state near the center is sampled in order to reliably determine the data state without being affected by jitter and waveform distortion even if they occur. .

[0007]

In this conventional code error correction apparatus, the state of the data is determined by continuously sampling the vicinity of the center of each data eight times to determine the state of the data. Since the state of the data is not determined over the area, there is a problem that the determination of the data state may be erroneous.

In this conventional example, since a clock for sampling is generated by an internal clock generation circuit, if the clock of the received data is converted, the internal clock generation unit must be adjusted accordingly. There is a problem that must be.

[0009]

According to the present invention, there is provided a code error correction apparatus comprising: a high-speed clock of an applied system transmitted via a transmission line; A digital signal composed of a plurality of bits is received, and the received digital signal is corrected on a bit-by-bit basis for an error of a logical value that should be originally present over the entire area period on the time axis of the one bit.

A code error correction device according to the present invention comprises a constrained clock of an applied system sent from a transmission unit via a transmission line, and one bit consisting of a predetermined plurality of time widths of the constrained clock. An error detection unit that receives a digital signal composed of a plurality of bits, and detects, in one clock unit of the high-speed clock, a place where the logic is changed at any number of high-speed clocks in one bit unit; The digital signal received by the output signal of the error detection unit is 1
An error correction unit that corrects a logical value error over a time axis period of the entire area of one bit in bit units, wherein the error detection unit receives the high-speed clock and the digital signal from the transmission line, A shift register for outputting an input clock signal when a high-speed clock is input, a previous clock signal one high-speed clock before the input clock signal, and a clock signal one high-speed clock after the input clock signal; And an exclusive OR circuit that outputs an erroneous clock time and a logical value signal from the three clock signals from the three clock signals. The error correction unit outputs the output signal from the exclusive OR circuit and the shift register. An OR circuit for outputting a logical sum signal based on the input clock signal of the above, And a dynamic flip-flop circuit for outputting a corrected said digital signal.

The code error correction apparatus according to the present invention comprises a high-speed clock of an applied system transmitted from a transmission unit via a transmission line, and one bit consisting of a predetermined plurality of time widths of the high-speed clock. A first dynamic flip-flop circuit for receiving a digital signal composed of a plurality of bits, a smoothing circuit for smoothing an output signal of the first dynamic flip-flop circuit, and a predetermined output signal of the smoothing circuit. A signal equal to or higher than the threshold as an input signal, and
A second dynamic flip-flop circuit for outputting a digital signal in which an error has been corrected to the logical value of the entire area on the time axis within the bit.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a time chart showing an operation in the first embodiment.

In FIG. 1, the code error correction apparatus according to the first embodiment includes a high-speed clock of an applied system transmitted from a transmission unit 3 via a transmission line 10 and a predetermined high-speed clock of the high-speed clock. One bit is formed with a time width of a plurality of (15 in the case of the first embodiment), a digital signal composed of a plurality of bits is received, and a high-speed clock number within a 1-bit unit is obtained. (1) If the logical value of one bit of the detected digital signal is "0", it is changed to "1", and if it is "1", it is changed to "0". An error detection unit 4 that performs
An error correction unit 5 is provided which corrects a logical value error of the digital signal received by the output signal from the error detection unit 4 in a one-bit unit over the entire area period of one bit.

The error detecting section 4 receives the high-speed clock and the digital signal from the transmission line 10, receives an input clock signal when the high-speed clock is input, a clock signal one clock before the input clock signal, and a clock signal one clock after the input clock signal. A shift register 41 for outputting a clock signal, and an E for outputting a logical value signal (error pulse) 7 at an erroneous clock time from three clock signals of the shift register 41.
An X-OR circuit 42, and the error correction unit 5
An OR circuit 51 that outputs a logical sum signal based on the error pulse 7 from the circuit 42 and the basic output signal that does not shift from the shift register 41, and a digital signal that has been error-corrected by the output signal of the OR circuit 51 and the high-speed clock. And a DF / F 52 for outputting.

That is, in the error detecting section 4 in the first embodiment, the logical value "A" at an arbitrary high-speed clock point and the logical values "B" and "C" at the high-speed clock points before and after the arbitrary high-speed clock point.
Are compared, the logical value “A” at any time is different from the logical value “B” at the previous time and the logical value “A” at any time
If the logical value “C” at the subsequent time is different from the logical value “C” at the subsequent time, the logical value “A” at an arbitrary time is determined as the error pulse 7 and error detection is performed. The next error correction unit 5 corrects the error by inverting the logical value “A” at an arbitrary point in time determined by the error detection unit 4 (“0” → “1” or “1” → “0”). Do.

Next, the operation of the first embodiment will be described with reference to FIGS.

The digital signal input to the digital input terminal 1 is oversampled by the high-speed clock in the transmission unit 3 and transmitted as sampling data to the transmission line 10, and contains a logical value error due to the influence of noise in the transmission line 10. The data is input to the error detector 4 as received sampling data. Originally, sampling data is read a plurality of times by a high-speed clock with respect to one bit of the input digital signal, so that “0” or “1” is read a plurality of times (the first bit).
In this embodiment, the logic signal train is continuous 15 times. The received sampling data in which an error has occurred in the transmission line 10 is a continuous digital signal sequence of “0” or “1”, and an isolated pulse (error pulse) of an incorrect logical value of “1” or “0” is present. Will exist.

In the error detecting section 4, as an example of a means for detecting the isolated pulse, a logical pulse signal for three consecutive high-speed clocks by a shift register 41 for three high-speed clocks, that is, a logical pulse signal at an arbitrary high-speed clock time point The logic pulse signals “A” and “B” and the logic pulse signals “A” and “C” and the logic pulse signals “A” and “C” are extracted by the EX-OR circuit 42 by extracting “A” and the logic pulse signals “B” and “C” before and after the high-speed clock.
Perform each comparison, and if both are different, EX-
An error pulse (“1” pulse for one high-speed clock) is output by the output of the OR circuit 41 and sent to the error correction unit 5 together with a high-speed clock and a logic pulse signal at an arbitrary time.

The error correction section 5 performs data inversion of “0” → “1” or “1” → “0” when there is an error pulse 7 with respect to a logical pulse signal of a high-speed clock at an arbitrary point in time. If there is no pulse 7, data is output without inversion. As an example, there is a method in which a logic pulse signal and an error pulse at an arbitrary high-speed clock are input to the EX-OR circuit 41 and the output is read out by the DF / F 52. However, DF / F52 in this case is EX-
This is nothing but a "whisker" generated at the output of the OR circuit 41.

The data output from the error correction section 5 is output from the digital signal output terminal 6 as code error corrected data.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. 4 is a time chart showing an operation in the second embodiment.

In FIG. 3, the code error correction apparatus according to the second embodiment includes a high-speed clock of the applied system transmitted from the transmission unit 3 via the transmission line 10 and the same clock as that of the first embodiment. An error correction unit 5a that receives the digital signal having the above configuration and corrects the logical value of the digital signal in units of 1 bit over the entire area period of 1 bit. The error correction unit 5a converts the digital signal from the transmission unit 10 A DF / F 53a received together with the high-speed clock, a smoothing circuit 54a of an RC circuit for smoothing the output of the DF / F 53a, and a signal having a logical value of "1" or more which is equal to or higher than a predetermined threshold of the output of the smoothing circuit 54a. And outputs a digital signal.

Next, the operation of the second embodiment will be described with reference to FIGS.

The digital signal input from the digital signal input terminal 1 is oversampled by the high-speed clock in the transmission unit 3 and transmitted as sampling data. The reception sampling including a logical value error due to the influence of noise on the transmission line 10 is performed. The data is input to the error correction unit 5a as data. Originally, the sampling data is read a plurality of times by a high-speed clock with respect to the input digital signal 1 bit as in the case of the first embodiment.
Or, “1” is plural times (15 times in the second embodiment).
Is a continuous digital signal sequence. Then, the received sampling data in which an error has occurred in the transmission line 10 is
An isolated pulse (error pulse) having an erroneous logical value of “1” or “0” exists in a continuous digital signal sequence of “0” or “1” for one high-speed clock. Therefore, the error correction unit 5a performs smoothing of the data by the smoothing circuit 54a of the RC circuit, and converts the isolated pulse into smoothed data 8 that does not reach the threshold, DF / F / F.
Retiming is performed in F55a, and the digital signal is output to the digital signal output terminal 6a as an output digital signal.

In the second embodiment, Jitt is performed at the time of rising and falling of a digital signal output in units of 1 bit.
However, the application system does not use the signal at this time.

[0027]

As described above, according to the present invention, the high-speed clock of the applied system transmitted via the transmission line and the time width of a predetermined plurality of high-speed clocks are used.
By receiving a digital signal composed of a plurality of bits by configuring bits and correcting the error of the logical value that should be originally over the entire area period on the time axis of 1 bit in units of 1 bit, Even if any one point in time is sampled with the high-speed clock over the entire area on the time axis within one bit of the corrected digital signal, the correct logical value is extracted, so that the application system using the received digital signal operates correctly. There is an effect that can be made.

Further, since there is no effect even if the frequency of the high-speed clock is changed, there is an effect that the same device can perform error correction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing an operation in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a time chart showing an operation in the second embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a diagram for explaining processing and an outline in the conventional example shown in FIG. 5;

[Description of Signs] 1 Digital signal input terminal 2 High-speed clock input terminal 3 Transmission unit 4 Error detection unit 5, 5a Error correction unit 6, 6a Digital signal output terminal 7 Error pulse 8 Smoothed data 10 Transmission paths 31, 52, 53a, 55a Dynamic flip-flop (DF / F) 41 shift register 42 EX-OR circuit 51 OR circuit 54a smoothing circuit

Claims (5)

[Claims] 1. A high-speed clock of an application system sent via a transmission line, and a digital signal composed of a plurality of bits, each bit having a predetermined time width corresponding to a plurality of the high-speed clocks. Wherein the digital signal received is corrected in a unit of one bit to correct an error of a logical value that should originally be present over the entire area period on the time axis of the one bit. 2. A high-speed clock of an applied system transmitted from a transmission unit via a transmission line, and one bit is formed by a predetermined plurality of time widths of the high-speed clock and is composed of a plurality of bits. An error detector for receiving a digital signal and detecting a logical change at any high-speed clock point in one bit unit for each high-speed clock; and an output signal of the error detector. An error correction unit for correcting a logical value error of the digital signal received by the digital signal over a time axis period of an entire area of 1 bit in 1 bit units. 3. The error detecting section receives the high-speed clock and the digital signal from the transmission line and receives an input clock signal at the time of inputting the high-speed clock and a previous clock which is one high-speed clock before the input clock signal. A shift register for outputting a signal and a clock signal after one high-speed clock after the input clock signal, and an exclusive logic for outputting a logic value signal at an incorrect clock time from the three clock signals from the shift register. 3. The code error correction device according to claim 2, further comprising a sum circuit. 4. An OR circuit for outputting an OR signal based on an output signal from the exclusive OR circuit and the input clock signal from the shift register.
4. The code error correction device according to claim 2, further comprising: a dynamic flip-flop circuit that outputs the digital signal error-corrected by the output signal of the OR circuit and the high-speed clock. 5. A high-speed clock of an application system transmitted from a transmission unit via a transmission line, and a plurality of bits forming one bit with a predetermined plurality of time widths of the high-speed clock. A first dynamic flip-flop circuit for receiving the digital signal, a smoothing circuit for smoothing an output signal of the first dynamic flip-flop circuit, and a signal having a predetermined threshold or more of the output signal of the smoothing circuit. A second dynamic flip-flop circuit that receives the high-speed clock as an input signal and outputs a digital signal in which a logical value error in all areas on the time axis within one bit is corrected. Error correction device.