JPH0528930B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to time division multiple access (hereinafter referred to as TDMA).
The present invention relates to a method for detecting a unique word that serves as a reference for reception timing from a received signal in a satellite communication system that performs.

〔overview〕

The present invention provides a method for detecting a unique word by comparing multiple series of received signals with a pattern of a predetermined predetermined length and detecting a unique word when a predetermined number or more of pits match the pattern. A unique word is detected by a simple calculation by adding the predetermined length and a number uniquely determined by the number of permissible error bits in pattern detection.

[Conventional technology]

In TDMA, each participating earth station communicates by transmitting burst signals on the satellite so that signals from other stations do not overlap. In a burst signal, a code called a unique word is inserted before the information code to be transmitted, and its detection signal serves as a reference for the reception timing of the burst signal.This allows the time position of the information code in the received burst signal to be You can know.

The unique word detection circuit includes a pattern comparison circuit and a threshold detection circuit. The pattern comparison circuit simultaneously compares the received signal with a unique word pattern of pattern length L that is expected to be detected in advance, and creates a total of L pieces of "1" if they match and "0" if they do not match. , this is a circuit that encodes this in binary numbers. Since the pattern comparison circuit compares L bits each time one new bit of the received signal is input, a comparison result can be obtained for each bit. The threshold detection circuit calculates a value L obtained by subtracting the number of pattern matches, which is the output of the pattern comparison circuit, and the number of error bits ε that can be tolerated when detecting a unique word from the unique word pattern length L.
-ε is compared in size, and when the number of pattern matches is equal to or greater than L-ε, it is determined that a unique word has been detected. By the way, in TDMA, the quadrature phase modulation method is often used as a modulation method.
In this case, since there are two columns of received signals, there are two pattern comparison circuits and two threshold detection circuits.
The number of pattern matches is input from two pattern comparison circuits. The number of these pattern matches is A, respectively.
If B, the threshold value detection circuit adds A+B before comparing the magnitudes, and sets A+B≧L−ε as the threshold value detection condition.

In the conventional threshold detection circuit, the magnitude comparison is started after all the additions A+B of the outputs of the two pattern comparison circuits are completed. Therefore, the delay time until detection was long. That is, the addition is the lowest 2 ⁰
Carry signals are sent to the higher digits in order, but the comparison is performed from the highest digit to the lowest digit, so the calculation for the lowest digit of A+B is completed, that is, all additions of A+B are completed. I couldn't start comparing the sizes until after that. The magnitude comparison circuit compares the most significant digits of L-ε and A+B, and if they are equal, it moves on to the comparison of the one lower digit, performs the comparison there, and if they are equal, it moves on to the comparison of the next lower digit. Move. If the two values are different and it is possible to determine whether they are large or small, the operation ends and the result is output, and comparison of lower digits is prohibited. However, the delay time until the result of the magnitude comparison is obtained is maximum when the comparison is performed at the least significant digit, and the maximum delay time of the conventional threshold detection circuit is
This is a very large value, which is the sum of the maximum delay times of both the adder circuit and the magnitude comparison circuit.

Next, a conventional threshold value detection circuit will be explained with reference to the drawings. FIG. 2 is a block diagram of a conventional threshold value detection circuit. This conventional example shows a case where the pattern matching number inputs A and B from the pattern comparison circuit are each 3 bits, and the threshold value L-ε is 4 bits.

The values of 2 ⁰ to 2 ^2nd place of pattern matching number A are as follows:
It is input to input terminals 101-103. Each of the pattern matching number B is 2 ⁰ to ^2. The second value is the input terminal 10.
4 to 106 are input. The threshold values L-ε are input to input terminals 107 to 110 at positions ²⁰ to ²³ , respectively. The threshold detection signal is output to the output terminal 111. Further, this threshold detection circuit includes full adders 1 to 3, comparators 11 to 14, and an OR circuit 15.
It is equipped with

The full adder 1 receives the input pattern matching number A,
The ^20th place value of B is added, and the resulting ^20th place value is output to the comparator 14, and a carry signal is output to the full adder 2. Full adder 2 adds the 2nd ^1st place value of pattern matching numbers A and B and the carry signal from full adder 1,
The resultant ^2-1st value is output to the comparator 13, and the carry signal is output to the full adder 3. The full adder 3 adds the ^2nd place value of pattern matching numbers A and B and the carry signal from the full adder 2, and sends the ^2nd place value to the comparator 12, which is the ^2nd place value. A carry signal is output to the comparator 11. Comparator 11 compares the carry signal of full adder 3, that is, the 2nd ^to 3rd digit value of A+B, and the ^{2nd to} 3rd digit value of threshold L-ε, and if the two values are different, A+B>L-ε If so, the comparison result "1" is outputted to the OR circuit 15, and at the same time, a comparison prohibition signal "0" is outputted to the comparator 12, thereby terminating the comparison. Further, if A+B<L-ε, the comparison result "0" is outputted to the OR circuit 15, and at the same time, a comparison prohibition signal "0" is outputted to the comparator 12, thereby terminating the comparison. If the two values are equal, they cannot be compared in size, so the determination of size is left to the ^2nd digit, so a comparison permission signal of ``1'' is sent to the comparator 12, and the comparison result is ``0'', which means that comparison is not possible. is output to the OR circuit 15. When the comparator 12 receives the comparison permission signal "1", the comparator 12 outputs 2 ² of A+B and L-ε.
If the two values are different, a comparison prohibition signal "0" is sent to the next lower comparator 13, and the comparison result is "1" or Either output "0" and end the size comparison, or if they are equal, output "0" indicating that comparison is not possible to the OR circuit 15, and output a comparison permission signal "1" to the comparator 13 one level lower. Leave the comparison to me. In this way, when the incomparability continues up to the comparator 13 in the ^21st place, the comparator 14 in the ^20th place inputs the comparison permission signal "1" from the higher comparator 13, and the comparator 14 in the 20th place Start comparing the size of ^{the 0th} place, and if A+B>L-ε, set the comparison result to "1" and the comparison prohibition signal "0"; if A+B<L-ε, set the comparison result to "0" and set the comparison prohibition signal to "0". is output to the OR circuit 15, and if A+B=L-ε, the comparison impossible signal is "0" and the comparison permission signal is "1".
and is output to the OR circuit 15. OR circuit 15
outputs "1" to the output terminal 111 if even one of the signals from the comparators 11 to 14 is "1", and outputs "0" if all the signals are "0". That is, it outputs "1" to the output terminal 111 when A+B≧L-ε, and outputs "0" when A+B<L-ε.

[Problem that the invention seeks to solve]

As explained above, the threshold value detection circuit used in the conventional unique word detection method logically correctly determines that A+B≧L−ε. By the way, the unique word detection signal is used to extract the information code placed after the unique word in the TDMA burst configuration, and the received signal must be delayed until the detection signal is output. . As mentioned above, the conventional threshold detection circuit starts comparing the magnitude with L-ε after the addition of A+B is completed, so the delay time until detection is A+B.
The detection delay time is generally long, especially as the unique word pattern length L becomes larger. . The longer the detection delay time, the more delay circuits that delay the received signal must be added.

Also, when using a soft decision method as the demodulation method, for example when performing 8-value soft decision, each of the two series of received signals becomes three columns, so a delay circuit is prepared for a total of six columns of received signals. There must be.
This goes against the trend of miniaturizing devices and reducing power consumption, and has been a major problem with conventional threshold detection circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a unique word detection method for solving the above problems and realizing a threshold detection circuit with a short detection delay time.

[Means for solving problems]

The unique word detection method of the present invention compares a received signal received as a plurality of signal sequences with a predetermined pattern of length L (L is a positive integer) for each received sequence, and In a unique word detection method, the received signal is determined to be a unique word when the sum of the number of matching bits, for example, A and B (in the case of two received sequences) exceeds a predetermined threshold. , the above ^judgment satisfies L ^{- ε} + The method is characterized in that a number X is determined, this number X is added to the sum of the number of matching bits, for example A+B, and the occurrence of a carry from the most significant digit due to this addition is detected.

[Effect]

The threshold value detection circuit of the present invention is configured to start the magnitude comparison before the addition of A+B is completed in order to shorten the large detection delay time. Conventional threshold detection circuits perform magnitude comparisons from the most significant digits to the least significant digits, so it is necessary to wait for the addition of the most significant digit of A+B to be completed, which increases the delay time. If a circuit is used that can perform magnitude comparison from the digits toward the upper digits, the magnitude comparison can be started without waiting for the addition of A+B to be completed, and the delay time can be shortened. Therefore, the present invention does not directly compare A+B and L-ε, but instead compares the numbers X and A+, which are created by adding an appropriate number to L-ε.
The addition with B is performed from the least significant digit to the most significant digit, and the presence or absence of a carry signal as a result of the addition at the most significant digit becomes the magnitude comparison result itself. Since X is a constant, it can be calculated and prepared in advance, and does not affect the detection delay time of the threshold detection circuit.

Here, the unique word pattern length L is assumed to be a value that can be expressed as an N-bit binary number. In other words, when 2 ^N-1 -1<L≦2 ^N -1 (N>0, L>0), the unique word pattern detection condition is A+B≧L-ε as mentioned above, but When a certain number X satisfying L-ε+X= ^2N is added to both sides, the unique word pattern detection condition becomes A+B+X≧ ^2N . This is when calculating A+B+X,
2 A "1" in ^{the N} position indicates detection, and a "0" indicates non-detection. The value of X is: X=2 ^N −(L−ε).

For example, when the unique word pattern length L=48 and the number of allowable error bits ε=6, since N=6, X=22, and the unique word pattern detection condition becomes A+B+22≦ ²⁶ .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a threshold value detection circuit according to an embodiment of the present invention. In this embodiment, the number of pattern matches A and B is 3 bits, as in the conventional example described above.
The added value X is assumed to be 4 bits.

Input terminals 101 to 103 are each full adder 1
~3 is connected. Input terminals 104-106 are also connected to full adders 1-3, respectively. Input terminals 107-110 are connected to full adders 4-7, respectively. Full adder 1 is connected to full adders 2 and 4. Full adder 2 is connected to full adders 3 and 5. Full adder 3 is connected to full adders 6 and 7. Full adder 7 is connected to output terminal 111.

Input terminals 101 to 103 are input with values of 2 ⁰ to ^{2 2} of the pattern matching number A, respectively. Input terminals 104 to 106 are input with values of 2 ⁰ to ^{2 2} of the pattern matching number A, respectively. Input terminal 107
.about.110 are input with the ^2.sup.0 to ^2.sup.2 values of the addition value X, respectively.

Full adders 1 to 3 add the pattern matching numbers A and B in the same way as in the conventional example described above, and add A+B of 2 ⁰ to 2 ³
A 4-bit signal is generated. That is, the full adder 1 receives the input pattern matching numbers A and B.
The ^20th place value of ^the result is added to the full adder circuit 4, and the carry signal is output to the full adder 2. The full adder 2 receives the input pattern matching number A
The ^21st place of B and the carry signal from the full adder 1 are added, and the resulting value of the ^21st place is output to the full adder 5, and the carry signal is output to the full adder 3. The full adder 3 is
Add the ^2nd place of the input pattern matching numbers A and B and the carry signal from full adder 2, and add the result 2 ²
The value of the place is sent to the full adder 6, and the carry signal is sent to the full adder 7.
Output to.

Full adder 4 receives the output of A+B from full adder 1.
The value of the ^20th place is added to the value of the ^20th place of adder X, and if there is a carry, a carry signal "1" is output to the full adder 5. The full adder 5 adds A+B, the ^21st -place value of the addition value X, and the carry signal from the full adder 4, and outputs it to the full adder 6 if there is a carry. Similarly, full adders 6 and 7 add the 2 ² and 2 ³ digits of A+B and adder X, respectively, and output the final carry signal to output terminal 111. The detection delay time of this embodiment, which operates in this manner, is the addition time of A+B plus two addition times. On the other hand, conventionally A+B
4 times of comparison time and OR circuit 1 in the addition time of
However, since there is generally little difference in the delay times of the comparator and the full adder, the delay time is greatly reduced.

In the above description, the case where the number of pattern matches is 3 bits has been exemplified, but the present invention can be similarly implemented with any number of bits. In particular, the longer the unique word pattern length L and the larger the number of bits of pattern matching, the greater the delay time reduction effect.

Furthermore, the present invention is not limited to the case where the modulation method is 4-phase, and the present invention can be implemented in the same manner when the modulation method is 8-phase, for example.

〔Effect of the invention〕

As described above, the unique word detection method of the present invention can be realized by a simple addition circuit of the unique word pattern threshold detection circuit of a TDMA device, and can shorten the time required for threshold detection. Therefore, the present invention reduces the size of the TDMA device.
This has the effect of reducing power consumption. In particular, this effect becomes greater as the unique word pattern length L becomes longer and the number of bits in the number of pattern matches increases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a threshold value detection circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional threshold value detection circuit. 1 to 6...Full adder, 11 to 14...Comparator,
15...OR circuit, 101-110...input terminal, 111...output terminal.

[Claims]

1 In the frame synchronization protection method used when performing frame synchronization for frame signal 111, clock signal 113 and frame count signal 1
15, shift register clock signal 1
17, and a plurality of binary operation units each responding to the shift register clock signal 117 are connected. Frame count signal 11
a shift register 121 that sequentially changes the numeral state corresponding to the synchronous/asynchronous state with 5; and a first numeral signal 122 of the shift register 121.
If A and the selection number of the first protection selection signal 123 match, the first detection means 127 that generates the first detection signal 125 and the second protection selection signal 129 are set to 1 as the number of backward protection stages. frame signal 1
11 is input or shift register 12
1 second digit signal 122B and second protection selection signal 1
a second detection means 133 that generates a second detection signal 131 when at least one of the selection numbers of 29 and 29 matches, and the first detection signal 125 or the second detection signal 131;
The timing of the clock signal 113 corresponds to