JP2626900B2 - Block synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for performing digital communication in the field of information processing or communication. The present invention relates to detection of block synchronization and establishment of synchronization of a signal encoded by a code including an error correction code.

[Conventional technology]

FIG. 4 shows a conventional block synchronization circuit. In this circuit, a syndrome calculation circuit 1 calculates a syndrome for each block based on a word synchronizing signal sent from a word counter 2 for input data. If the calculated syndrome is not 0, an error pulse is sent.
The protection circuit 3 inputs this error pulse, and when the error pulse is continuously transmitted N times, which is a predetermined number of forward protection stages, the protection circuit 3 determines that the block synchronization has not been established and changes the phase of the word counter 2. Shift one bit. Further, when the syndrome calculated by the syndrome calculation circuit 1 is 0, which is a value indicating that synchronization has been established continuously M times, which is the number of backward protection stages, the protection circuit 3 determines that block synchronization has been established.

To explain this in detail, the received signal is _{... a -2, a -1, a} 0, a 1, a 2, ... a n-1, a n, a ..., signal the correct block a _0, a ₁ ,... A _n−1 ,, the polynomial expression of the received signal is R ₀ (X) = a ₀ X ⁿ⁻¹ + a ₁ X ⁿ⁻² ... + A _n−2 X + a _n−1 (1) Become. Here, + indicates addition of mod2. Similarly, polynomial expression of received signal at initial phase shifted by k bits
R _k (X) becomes R _k (X) = _ak X ^n-1 + _{ak + 1} X ^n-2 + ... + ... an _{+ k-1} X + a _{n + k-1} (2).

Assuming that the root of the generator polynomial G (x) = 0 is α, the value of the syndrome is a value obtained by substituting x = α into the reception polynomial. Therefore, the syndrome _{S 0 = R 0 (α)} = a 0 α n-1 + a 1 α -2 + ... + a n-2 α + a n-1 = 0 is (3) in the correct initial phase. That is, in this case, 0 is a value indicating the establishment of synchronization.

Also, the syndrome in one bit shifted initial phase _{S +1 = R +1 (α)} = a 1 α n-1 + a 2 α n-2 + ... + a n-1 α + a n = R 0 (α) α + a n + A ₀ α ⁿ = R ₀ (α) α + (a _n + a ₀ ) (∵α ⁿ = 1) = (a _n + a ₀ ) α ⁰ (4), and _{if an} = a ₀ , the syndrome is 0 . Similarly, the syndrome at the phase shifted by one bit is S _-1 = (a _-1 + a _n-1 ) α ^n-1 (5) S _-2 = (a _-2 + a _n-2 ) α ^n-1 + (a _{-1 + a n-1) α} n-2 (6) S +2 = (a 0 + a n) α 1 + (a 1 + a n + 1) α 0 become (7).

Therefore, when the initial phase is shifted by 1 and 2 bits before and after, the syndrome is 0 with a probability of 1/2 and 1/4, respectively, that is, the value is the same as the value indicating the establishment of synchronization. In general, a block synchronization circuit has a backward protection circuit, and establishes block synchronization when the number of blocks in which the syndrome is a value indicating the establishment of synchronization continues M times. Therefore, erroneous synchronization occurs with the probability of (1/2) ^M , (1/4) ^M ,. As a means for preventing this erroneous synchronization, there is a method of inverting a part of the signal on the transmission side. For example
Inverting a _i gives the syndrome S ₀ ′ with the correct initial phase
Is S ₀ ′ = S ₀ + α ^n-1-i = α ^n-1-i . In this case, the syndrome at the initial phase shifted by 1 bit is α
^{n−1−i ± 1} , and the erroneous synchronization probability can be reduced. In this case, the value indicating the establishment of synchronization is α ^n-1-i . When synchronization is established, _ai is inverted on the receiving side. Therefore, if no error has occurred, the syndrome is 0. However, even in this case, erroneous synchronization may occur due to an error or the like occurring in the transmission path, and a backward protection circuit is required.

When erroneous synchronization occurs, the conventional circuit counts error pulses in the forward protection circuit, and when N error pulses occur consecutively N times, it is determined to be asynchronous and block synchronization is performed again.

[Problems to be solved by the invention]

Here, when a signal is a multi-level signal and a plurality of m-sequence signals whose initial phases match each other are input, the operation of establishing synchronization as described above is performed with the m-sequence signals in the same initial phase. Then, the time required to establish the synchronization is equal to the time required for one sequence.

It is an object of the present invention to provide a scheme for establishing synchronization in a shorter time by taking advantage of this property when a plurality of m-sequence signals having the same initial phase are input.

[Means for solving the problem]

The present invention includes, for each sequence, a circuit that receives an m-sequence signal (m is an integer of 2 or more) that includes an error correction code and is encoded and has the same initial phase, and calculates a syndrome from one initial phase; In a block synchronization system provided with means for detecting that the syndrome calculated by this circuit is a value indicating the establishment of synchronization continuously M times (M is an integer of 1 or more) for all the series and establishing synchronization. Means for randomly setting the phases of a plurality of streams in a state where synchronization has not been established, and m-sequences when the syndrome calculated by the circuit reaches a value indicating synchronization establishment for one of the plurality of streams. And a means for adjusting the phase to the phase of this one series.

[Action]

For a plurality m of series, at least two or more series,
First, the syndrome is calculated and detected while the phase is randomly set and the phase is sequentially changed. As a result, when the syndrome calculation result of any of the systems indicates a value indicating the establishment of synchronization, it is determined that the system has the correct phase, and the phase of the other system is made to match the system. By doing this, rather than searching for the correct phase with all the systems in phase,
Since a correct phase can be found with a high probability, synchronization can be established in a short time as a possibility.

〔Example〕

FIG. 1 is a block diagram of the circuit of the first embodiment of the present invention. In this circuit, m-sequence signals that include an error correction code and are coded and have the same initial phase are input to terminals 11 to 1m. Each sequence is provided with syndrome calculation circuits 21 to 2m that receive this signal and calculate a syndrome from one initial phase. The calculation result of the syndrome is sent to terminals 31 to 3m. A frame pulse selection circuit 5 is provided which includes a means for inputting the syndrome calculated by this circuit for all of the series, and for establishing synchronization when the syndrome has a value indicating synchronization establishment for each series continuously M times.

As an example, m = 4 or 8, and M = 1, 2 or 4. Here, the apparatus of the present invention includes a first frame counter 6 including means for counting clock signals and sequentially changing phases from a phase set at random for a plurality of streams, and in a state where synchronization is not established. The frame pulse selection circuit 5 selects the output of the frame counter 6 and sends it to each of the syndrome calculation circuits 21 to 2m. On the other hand, a second frame counter 7 that counts the same clock signal in synchronization with the frame counter 6 is provided. The second frame counter 7 receives the result of the syndrome calculation of each series, and when the calculated syndrome becomes a value indicating the establishment of synchronization for one of the series, m
Means for generating a frame pulse by adjusting the phase of all the series to the phase of this one series is included. When the calculated syndrome reaches a value indicating synchronization establishment for one of the series, the frame pulse selection circuit 5
Detects this, selects the output of the frame counter 7 and sends it to each of the syndrome calculation circuits 21-2m.

FIG. 2 is a time chart showing this operation. This figure explains the operation of establishing synchronization with m = 4 and M = 2. When a value indicating the establishment of synchronization as a syndrome is detected in the fourth signal (4), the signals (1) to (3) are output. ) Is adjusted to the phase of this signal (4), and at the position of *, the syndrome becomes a value indicating the establishment of synchronization. This is repeated 2
Times (= M) is detected and synchronization is established.

FIG. 3 is a time chart showing another operation example of the embodiment of the present invention. In this example, when a signal indicating synchronization establishment is detected as a syndrome M = 2 consecutive times for the signal (4), the other signals (1) to (3) are adjusted to the phase of the signal (4). Therefore, synchronization can be established in the same time as in the previous example.

As a practical example, it was implemented on 8 sequences of 256 QAM signals.

As described above, the probability that the correct synchronization phase can be detected is increased by m times, and the time required for average synchronization establishment is reduced by 1 /.
m. Although the maximum time required for establishing synchronization is the same as that of the conventional example, the probability that the maximum time appears is extremely small.

In the above example, the syndrome calculation result is input for all m sequences, and it is detected that one of the m sequences has a value indicating the establishment of synchronization. By detecting that one of the values indicates the establishment of the synchronization, the time required for the average establishment of the synchronization can be reduced to 1 / m '.

〔The invention's effect〕

As described above, according to the present invention, the time required to establish synchronization is reduced, and the time during which communication is disabled in an asynchronous state can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a time chart for explaining the operation. FIG. 3 is a time chart for explaining another operation example. FIG. 4 is a block diagram of a conventional apparatus. 11 to 1 m: m-sequence signal input terminal, 21 to 2 m: syndrome calculation circuit, 31 to 3 m: terminal from which the syndrome calculation result is transmitted, 5: frame pulse selection circuit, 6: first frame Counter, 7 ... second frame counter.

Claims (1)

(57) [Claims] 1. A block synchronization system comprising a circuit for receiving a plurality of m-sequence signals including an error correction code and having the same initial phase and calculating a syndrome from one initial phase in each of the series. In a state where is not established, a circuit for calculating a syndrome from a plurality of initial phases different from each other for a plurality of streams, and when the syndrome calculated by the circuit for calculating the value indicates synchronization establishment for one of the plurality of streams, means for adjusting the phase of the m-sequence signal to the phase of this one series; and means for establishing synchronization when the calculated syndrome has a value indicating the establishment of synchronization continuously and M times for all of the series. A block synchronization method.