RU2784953C1 - Stable code framing method when applying hard decisions - Google Patents

Abstract

FIELD: communication technology.

SUBSTANCE: invention relates to communication technology. The effect is achieved due to the method for code frame synchronization for the concatenated code when applying hard decisions, which relates to discrete information transmission systems. The input sequence consists of several consecutive words, each of which is a bitwise modulo two sum of an error-correcting cyclic code, a numbering sequence, and a phasing sequence. In order to exclude possible triggering of false block synchronization, at the end of each numbering sequence, the value of its match counter is compared with all match counters of the remaining labels. If, at the end of each numbering sequence, the value of its match counter exceeds or becomes equal to the threshold value and exceeds the value of any match counter of all marks, then a decision is made on code framing of the input sequence, while resetting all match counters. To maximally exclude false synchronization of blocks, after determining the correct synchronization, a counter is started for a period of time corresponding to the duration of the transmission of one block, and if at the end of the count confirmation of the correct synchronization of the block comes, then during further transmission of blocks, all possible false synchronization responses are ignored inside the true blocks from the code blocks. words, and with each next transmission of the block, the correct synchronization of the block is confirmed.

EFFECT: increasing the reliability of the received information by increasing the probability of correct block synchronization.

2 cl, 3 tbl

Description

The invention relates to communication technology for discrete information transmission systems and can be used in noise-immune information protection systems that use correction codes, in particular concatenated codes.

When developing devices for code frame synchronization, an urgent task is to increase the probability of establishing correct synchronization, and, consequently, to increase the probability of receiving reliable information in communication channels with a high level of interference. Correct synchronization is understood as synchronization that ensures the reception of reliable information.

In code frame synchronization devices, synchronization features are transmitted in words of an error-correcting code, while code redundancy is used and therefore the transmission of additional synchronization symbols is not required. In this case, synchronization is provided by repeated repetition of synchronization features in different words of the inner code of the concatenated code.

The proposed method of code frame synchronization is aimed at increasing the probability of establishing correct synchronization in communication channels with a high level of interference.

Closest to the proposed method is the method of code frame synchronization for concatenated code when using hard decisions (prototype) [RF Patent No. 2759801 IPC H04L 7/08, H03L 7/183, publ. 11/18/2021, Bull. No. 32). This method consists in the fact that the received input sequence, consisting of several successive words, each of which is a bitwise sum modulo two of the error-correcting cyclic code, the numbering sequence and the phasing sequence, is first multiplied by the test polynomial of the error-correcting cyclic code and, as a result of multiplication, the sum of the syndromes of the error-correcting cyclic code, the numbering sequence and the phasing sequence is obtained. Then the resulting sum is multiplied by the check polynomial of the numbering sequence and the sum of the syndromes of the noise-correcting cyclic code and the phasing sequence is obtained, the syndrome of the phasing sequence is subtracted from this sum and the syndrome of the noise-correcting cyclic code is obtained, which can correspond to one numbering sequence or several numbering sequences. Each bit in a continuous sequence equal to the number of bits in the codeword of the cyclic error-correcting code is assigned its own label, which is repeated constantly after a period of time corresponding to the transmission of one codeword. Therefore, such labels define the boundaries of the words of the cyclic error code and the words formed at the junction of two adjacent words of the cyclic error code. The block of words of the cyclic error code and the blocks of words formed at the junction of two adjacent words of the cyclic error code are assigned their own synchronized numbering sequence counters and their match counters. If the number recorded in the corresponding match counter exceeds or equals the threshold value, at the end of this numbering sequence, a decision is made on the code framing of the input sequence. Moreover, the threshold value of the number of code words in the synchronizing sequence is equal to the minimum set of code words required for block decoding, and synchronization is carried out by code words with the number of errors in them not more than the correcting ability of the code words obtained after removing the synchronizing symbols from the input sequence. For each block word corresponding to its label, synchronized counters form in parallel a complete set of numbering sequences. The values of these synchronized counters are incremented in parallel by one after a period of time corresponding to the transmission of one codeword. When the synchronized counters reach their maximum value, the next value of the counters corresponds to their initial value, and the cycle time of the synchronized counter is equal to the duration of the numbering sequence. For each synchronized counter of one specific numbering sequence, there is a different set of hit counters for all different labels. The values of each synchronized counter from the full set of numbering sequences for each label are compared by hardware in parallel with the numbers of numbering sequences for the corresponding word of the input sequence that is currently being analyzed. If the word number of the input sequence matches the value of the synchronized counter of the numbering sequence, the value of their coincidence counter is increased by one, if the number recorded in the corresponding match counter exceeds or equals the threshold value, after the end of this numbering sequence, a decision is made on code framing of the input sequence. In this case, all match counters are reset to their original state. If, at the end of the synchronizing sequence, its match counter corresponding to the label of certain words of the input sequence has not reached the threshold value of the hit counter, then only this hit counter is reset.

The disadvantage of the prototype is the possible operation of false synchronization for blocks, which reduces the likelihood of establishing the correct synchronization in the communication channels and leads to a decrease in the reliability of the received information.

The aim of the invention is to increase the reliability of the received information by increasing the probability of correct block synchronization.

What is new is that, in order to exclude possible triggering of false block synchronization, at the end of each numbering sequence, this value of the match counter is compared and, if the number recorded in this match counter is exceeded or equal, the threshold value with all match counters of all labels, that is, with 991 counter. If in any of these counters the value is equal to or greater than the value of this matching counter, then at the end of this numbering sequence, no decision is made about the code framing of the input sequence, while only the matching counter of this numbering sequence is reset, and the correct operation continues. block synchronization. If, at the end of the synchronizing sequence, its match counter corresponding to the label of certain words of the input sequence has not reached the threshold value of the hit counter, then only this hit counter is reset.

If, at the end of each numbering sequence, the value of its match counter exceeds or becomes equal to the threshold value and exceeds the value of any match counter of all marks, then a decision is made on code framing of the input sequence, while resetting all match counters.

What is also new is that, in order to maximally exclude false synchronization of blocks, after determining the correct synchronization, a counter is started for the duration of the transmission of one block.

If, at the end of the count, confirmation of the correct synchronization of the block is received, then during the further transmission of blocks, all possible false synchronization of blocks is ignored, and with each next transmission of the block, the correct synchronization of the block is confirmed. If the next confirmation of the correct block synchronization does not arrive, then this means either the end of the message transmission, or, in the worst case, the loss of the block, in which case the synchronization algorithm switches to searching for the correct block synchronization and a new confirmation of the correct block synchronization.

The proposed code framing method for concatenated code with hard decisions works as follows.

On the transmitting side, as output information, a sequence with ₁ ⊕ c _2i ⊕ c _3n is formed, which is a bitwise sum modulo two of three sequences: a sequence of internal binary codes of a concatenated code with ₁ , a numbering binary sequence c _2i =c ₂₁ c ₂₂ c ₂₃ ... c _2n and a phasing sequence c _3n =с ₃ s ₃ s ₃ … s ₃ that violates the cyclic properties of the source code and consists of repeating cyclic sequences, where n is the number of BCH code words, c _2i is the numbering sequence for the i-th BCH word.

To obtain a sequence with ₁ on the transmitting side, the original information of k m-ary (m>1) symbols is encoded with an m-ary error-correcting code, for example, an m-ary Reed-Solomon (PC) error-correcting code. The PC code is an outer code or a first stage code of an error-correcting concatenation code.

As a result of such encoding of the initial information, a block of code words PC (N, k) is obtained, the information length of which k is equal to the word PC, and the block length is N symbols.

Next, the block of information, consisting of words PC, is encoded with a binary code, for example, a binary BCH code with a check polynomial h ₁ (x). The BCH code is an inner code or a code of the second stage of the error-correcting concatenation code. The BCH code word has the following parameters: n ₁ - block length of the code, k ₁ - information length of the code. As a result of encoding a block of PC words with a BCH code, a block of N binary words of the BCH code (n ₁ , k ₁ ) is obtained, which is a sequence with ₁ .

Next, the words of the BCH code are summed modulo two with the numbering sequence c _2i . As a numbering sequence, a binary code with block length n ₁ and information length k ₂ is chosen, for example, a Reed-Muller (RM) code of the first order (maximum period sequence) with a check polynomial h ₂ (x). The information length k ₂ of the RM code corresponds to the binary notation of the BCH word numbers. A one-to-one correspondence is established between the numbers of BCH words in the concatenated code and the information part of the numbering sequence. The first BCH word is summed modulo two with the sequence obtained by encoding the binary notation of the first BCH word number with the PM code, the second BCH word is summed modulo two with the sequence obtained by encoding the binary notation of the second BCH word number with the PM code, and so on. Such a summation operation is performed on all words of the BCH code. If the check polynomials h ₁ (x) and h ₂ (x) of the summed BCH and RM codes are coprime and are divisors of the binomial x ⁿ¹ +1, as a result of the summation, N words of the cyclic BCH code with length n ₁ and information length k ₁ + _k2 . This code will correct errors, the number of which

e≤<r/log ₂ (n ₁ +1),

where r=n ₁ -k ₁ -k ₂ is the number of check symbols of the code.

The third sequence with ₃ to which the BCH words are summed will be a constant sequence of length n ₁ bits for all words. Such a sequence can be any sequence that is not a BCH code word, for example, the sequence 10000...000.

In real channels, interference is possible, which can be considered as a sequence with ₄ , the presence of units in which corresponds to the placement of errors in words. For error-free words, the sequence with ₄ contains only zeros.

Consider the operation of the code frame synchronization method for a concatenated code when applying hard decisions using the example of a two-stage concatenated code [PC(32, 16, 17), BCH(31, 16, 7)]. In the encoder, the original block of information of 256 bits is divided into two blocks of 16×8 bits, each of which is encoded with a PC code. The PC encoder typically performs coding by multiplying the information vector by the code generator matrix. The operation is performed in the Galois field GF(2 ⁸ ) in accordance with the generating polynomial

P (x) \u003d x ⁸ + x ⁶ + x ³ + x ² +1

Thirty-two eight-bit PC words result from encoding a 16×8 block with a PC code. Next, the words from the two blocks are grouped by two and receive thirty-two sixteen-bit words, which are encoded with a BCH code.

BCH encoding is carried out in accordance with the check polynomial

h ₁ (x) \u003d x ¹⁶ + x ¹² + x ¹¹ + x ¹⁰ + x ⁹ + x ⁴ +1

The polynomial is used as a check polynomial for the numbering sequence

h ₂ (x) \u003d x ⁵ + x ² +1

Information in the form of a sequence with ₁ ⊕ c _2i ⊕ c _3n ⊕ c ₄ , formed from four sequences, is fed to the information input of the code frame synchronization device. Usually this sequence passes through a correction device (CU). KU is designed to synchronize bits of information with the frequency of reception and restore the shape of these bits in case of possible distortion. A variant of the KU, its block diagram and a description of the functioning are given in the source [V.I. Shlyapobergsky. Fundamentals of Discrete Message Transmission Technique. M .: "Communication", 1973, p. 275, fig. 5.15]. Next, the sequence is recorded in the information storage device. Simultaneously, this sequence passes through two Huffman filters. In the information storage device, the sequence is written to one of two random access memories (RAM) until the end of the block of BCH words is determined, which must correspond to the correct definition of code frame synchronization. After that, the drive control circuit will start writing subsequent information to another RAM, and reading information from the previous RAM will begin for further processing and decoding operations. The use of an information storage device containing two RAMs makes it possible to apply a pipeline method of information processing, providing simultaneous recording and reading of information from the information storage device, which increases the speed of the code frame synchronization method.

In Huffman filters, the sequence is multiplied by the check polynomials of the BCH and PM codes h ₁ (x) and h ₂ (x). Thus, in the first Huffman filter, the syndrome of the word of the BCH code of the sequence c ₁ is calculated, and in the second Huffman filter, the syndrome of the PM code of the sequence c _2i .

For an unmistakable word, the code syndrome is zero, and the combination b ₀ corresponding to the sequence c ₃ transformed in Huffman filters will be written in the syndrome register.

For words with errors, the correction of which is possible within the correcting ability of the code, a combination from a certain set {b _i } corresponding to the sequence from ₃ ⊕ с ₄ transformed in Huffman filters and uniquely determining the combination of errors will be written in the syndrome register. Hard decoding of the received sequence allows to correct no more than (dl)/2 errors, where d is the minimum code distance of BCH code words.

The decoder block, when a combination b ₀ or a combination from the set {b _i } is found in the syndrome register, outputs to the input of the modulo adder block two corresponding combinations for error correction.

At this moment, the register of the second Huffman filter contains a binary combination of numbers that uniquely corresponds to the sequence c _2i , since the sequence c ₁ is removed by the first Huffman filter, and the sequence c ₃ is constant.

This binary combination of numbers from the output of the register is fed to another input of the modulo two adder block. In the block of modulo two adders, the bits of the considered combination of numbers are corrected so that its output is a binary combination corresponding to the supposed true number of the BCH code word. The syndrome combinations that are recognized by the decoder block are obtained by calculating the syndrome for each of the possible error combinations. An example of building a block of decoders is presented in the source [J. Clark, Jr., J. Kane. Error correction coding in digital communication systems: TRANS. from English. - M.: Radio and communication, 1987, p. 96-101].

As a result of summing the BCH code words (31, 16, 7) with the numbering sequence, BCH code words (31, 21, 5) are obtained. For BCH code words (31, 21, 5), syndromes are calculated for unambiguous correction of their numbers up to one error per word. For the BCH(31, 21, 5) code, the syndrome corresponds to ten bits. Therefore, only double and triple errors in a word correspond to C ² ₃₁ + C ³ ₃₁ =465+4495=4960 of the variant. Moreover, 527 triple error syndromes correspond to five variants of code words and 465 double and triple error syndromes correspond to one version of the code word for a double error and four variants of the code word for triple errors. Therefore, the transformed words corresponding to the 1860 triple error codeword variants may give a spurious number as a double error codeword when synchronized. The corrected word numbers of the BCH code from the output of the modulo two adder block are fed in parallel to the input of the number comparison circuit.

The number comparison circuit contains thirty-one lists for thirty-two synchronized counters of the full set of numbering sequences and 31×32=992 match counters. In the proposed method, all synchronization options for numbering sequences and words of the input sequence are taken into account. Each list contains thirty-two common synchronized counters and their corresponding thirty-two match counters with the possibility of writing to each of them a maximum number equal to N, where N is the number of BCH code words in the block. Such a number of counters in each list excludes false overwriting of BCH code words during code synchronization. To decode a concatenated code block, a set of BCH code words of at least the value M is required, where M is the minimum number of BCH code words sufficient to decode the block. As L increases, where L is the word count threshold for correct code alignment, the probability of correct code frame alignment and the probability of false frame alignment decrease. To receive a concatenated code block, it is necessary to perform proper code framing and perform decoding of the concatenated code block. Therefore, for the threshold value of the correct code synchronization for word synchronization with the maximum possible number of errors corrected by hard decisions, the optimal solution is L equal to M. For a two-stage concatenated code [PC(32, 16, 17), BCH(31, 16, 7)] the values of L and M are sixteen.

With KU, the clock pulses enter the BCH word length distributor based on the Johnson counter. An example of the implementation of a variant of the distributor based on the Johnson counter is given in the source [V.L. Awl. Popular digital circuits. Directory. Moscow. Metallurgy, 1988, p. 240, fig. 2.40]. The interval between pulses at each output of the Johnson counter distributor corresponds to the boundaries of BCH words or words formed at the junction of two BCH words, and the pulse itself serves as a label. Comparison of numbers of numbering sequences is carried out only within the list of one label corresponding to the boundaries of the words whose numbers are being analyzed at the moment. Moreover, the comparison of the numbers of the input sequence and the values of the synchronized counters of the full set of numbering sequences within each list is carried out in parallel by hardware. The operation of finding equal values of synchronized counters to the corrected numbers of the numbering sequences is carried out and the values of their match counters are increased by one. A variant of the complete set of numbering sequences for one label can be represented as follows: the first synchronized counter has a value of 00000, the value of the second synchronized counter is one more than the value of the first synchronized counter, that is, 00001, the value of the third synchronized counter is one more than the value of the second synchronized counter, that is 00010 and so on. Therefore, the value of the thirty-second synchronized counter for this label will be 11111. After a certain interval, corresponding to the time of transmission of one code word, the values of the synchronized counters are incremented in parallel by one, and this label serves as a cycle. After a time interval corresponding to the duration of the transmission of thirty-one code words, the values of these synchronization counters will be:

11111, 11110, 11101, 11100, ..., 00010, 00001.00000.

For the full set of numbering sequences, one synchronized counter can be applied, and the values for the remaining thirty-one synchronized counters can be obtained by summing. For example, the value of the second synchronized counter is obtained by adding one (00001) and the value of the first synchronized counter, the value of the third synchronized counter is obtained by adding the number two (00010) and the value of the first synchronized counter, and so on. The value of the thirty-second synchronized counter is obtained by summing the number thirty-one (11111) and the value of the first synchronized counter.

For a code word with two or three input sequence errors, each of the five numbering sequence number options within the list for this word is compared in parallel with the values of the synchronized counters of the full set of numbering sequences, and if there are comparisons, then the values for all corresponding match counters in one cycle are increased by unit.

In order to exclude possible triggering of false synchronization of blocks at the end of each numbering sequence, this value of the match counter is compared if the number recorded in this match counter exceeds or equals the threshold value with all match counters of all labels, i.e. with 991 counters. If in any of these counters the value is equal to or greater than the value of the match counter at the end of this numbering sequence, then code framing of the input sequence is not performed, while only the match counter of this numbering sequence is reset and the correct block synchronization operation continues. If, at the end of the synchronizing sequence, its match counter corresponding to the label of certain words of the input sequence has not reached the threshold value of the hit counter, then only this hit counter is reset.

The algorithm for comparing, at the end of each numbering sequence, the values of their match counters with the remaining 991 label match counters can be as follows. When the synchronous counter counts to the end, then the value of its hit counter for the corresponding label is compared with a threshold value. If the value of this match counter is equal to or greater than the threshold value, then a logical "1" marker is generated. When the value of this match counter is less than the threshold value, then for it and for the match counters of the remaining 991 match counters, logical "0" markers are formed. Each label has a full set of 32 synchronous counters. Each value of their match counters is compared in pairs with each other. The value of the first hit counter is compared with the value of the second hit counter, the value of the third hit counter is compared with the value of the fourth hit counter, and so on, the value of the thirty-first hit counter is compared with the value of the thirty-second hit counter. After comparison, the output of the circuit receives a larger value of the counter of matches with its marker. For one label, 16 pairs of coincidence counters are compared at the first stage, and 8 pairs, 4 pairs, 2 pairs, and one pair of coincidence counters are compared, respectively, at subsequent stages. Each label requires five stages of comparisons, and then the largest value of the counter of matches with its marker is sent to the output of its comparison circuit. Then, in a similar way, the coincidence counters for thirty-one labels are compared, which requires five more stages of comparisons. If there is a logical "1" marker at the output of the common comparison circuit, then this means the definition of code frame synchronization. If there is a logical "0" marker at the output of the comparison circuit, then this means the absence of code frame synchronization.

Therefore, if, at the end of each numbering sequence, the value of its match counter exceeds or becomes equal to the number recorded in this match counter, the threshold value and, when compared, is greater than the value of any match counter of all labels, then a decision is made about the correct code framing of the input sequence, while reset all match counters.

In order to maximally exclude false synchronization of blocks, after determining the correct code frame synchronization, a counter is started for a period of time corresponding to the duration of the transmission of one block. If, at the end of the count, confirmation of the correct code frame synchronization of the block arrives, then during the further transmission of blocks, all possible false synchronization of blocks within the transmitted block is ignored, that is, their match counters are reset, and with each next transmission of the block, the correct code frame synchronization of the block is confirmed. If the next confirmation of the correct code frame synchronization of the block does not arrive, then this means either the end of the message transmission, or, in the worst case, the loss of the block, in which case the synchronization algorithm switches to searching for the correct block synchronization and a new confirmation of the correct block synchronization.

The proposed method of code framing for concatenated code when using hard decisions compared with the prototype has a higher probability of correct block synchronization.

The probability distribution density of the voltage value when transmitting a zero symbol at the output of a matched filter for a coherent phase modulation system is given in [J. Clark, J. Kane. Error correction coding in digital communication systems; per. from English. - M: Radio and communication, 1987, p. 20, fig. 1.3.].

The bit error probability for hard decisions is equal to the probability that q>0 and is given by

which corresponds to Fig. 1.3 the area of the figure under the curve p(q|0) to the x-axis q to the right of its zero.

- интеграл вероятностей [Г.Корн, Т. Корн. Справочник по математике для научных работников и инженеров М.: Издательство «Наука», 1973, с. 578].

- integral of probabilities [G. Korn, T. Korn. Handbook of mathematics for scientists and engineers, Moscow: Nauka Publishing House, 1973, p. 578].

- отношение сигнал/шум.

- signal-to-noise ratio.

The probability of out-of-sync blocks of information can be determined by the following formula

where

Р(≤t) - probability of synchronized code words with t correctable errors,

L - threshold value of the number of code words for block synchronization,

i - sequence 0,1,…, (L-1).

where

p - average probability of errors per bit, determined by formula (1),

t is the maximum number of errors that can be corrected in each word,

j - sequence 0, 1, …, t,

n is the number of bits in the BCH codeword.

The upper bound on the probability of one variant of false synchronizations at the junctions of code words for shifted blocks can be estimated by the following formula

The upper bound on the probability of all variants of false synchronizations at the junctions of code words for shifted blocks can be estimated by the following formula

- вероятность номера, соответствующего слову ложной нумерующей последовательности,where

- the probability of the number corresponding to the word of the false numbering sequence,

n is the number of bits in the codeword,

L - threshold value of the number of code words for block synchronization,

N - the number of words in the block,

i - sequence 0, 1, …, (L-1),

k - sequence 0,1, ..., (L-1).

The probability of correct block synchronization for a prototype can be estimated by the following formula

Table 1 shows the values of the probabilities of correct block synchronization for the prototype, depending on the signal-to-noise ratio.

The probability of correct block synchronization for the proposed method of stable code framing when applying hard decisions can be estimated by the following formula

where Р _ns is the probability of unsynchronized blocks of information,

Р _ls - the probability of all variants of false synchronization of information blocks,

n-1 - the number of variants of false numbering sequences,

n is the number of bits in each codeword of the block,

Р _ls0 - probability of false synchronization for one variant of false numbering sequences of information,

P _lssm is the probability of one variant of false synchronization at the junctions of code words for shifted blocks, is determined by formula (4),

P _total - the probability for one variant of the suppression of false leading synchronization sequences at the junctions of code words for offset blocks with correct synchronization sequences. False advanced synchronization sequences at the junctions of code words exceed the values of numbers in words compared to the numbers of code words of the true code sequence, therefore, the end of synchronization of these false sequences occurs before the end of the true code sequence.

where

L - threshold value of the number of code words for block synchronization,

N - the number of words in the block,

i - sequence 0, 1, …, (L-1),

j - sequence 0, 1, …, (L-1),

c - sequence 0, 1, ..., (L-1).

Р _total - the probability of one variant of suppression by false delayed synchronization sequences at the junctions of code words for shifted blocks of correct synchronization sequences. False delayed synchronization sequences at codeword junctions have smaller word numbers compared to the codeword numbers of the true code sequence, so the end of these false synchronization sequences occurs later than the end of the true code sequence.

where

L - threshold value of the number of code words for block synchronization,

N - the number of words in the block,

i - sequence 0, 1, …, (L-1),

j - sequence 0, 1, …, (L-1),

k - sequence 0, 1, …, L.

Table 2 shows the values of the probability of correct block synchronization for the proposed method when suppressing false synchronization by sequences of correct block synchronization, depending on the signal-to-noise ratio.

Table 3 shows the probability of correct block synchronization for the proposed method when suppressing false synchronization with confirmations of correct block synchronization, depending on the signal-to-noise ratio.

From the values of the probability of correct block synchronization given above in the tables, it follows that the probability of correct block synchronization for the proposed method is higher than the probability of correct block synchronization for the prototype.

Achievable technical result of the proposed method of stable code frame synchronization when applying hard decisions is to increase the reliability of the received information by increasing the probability of correct block synchronization.

Claims (2)

1. The method of stable code frame synchronization when applying hard decisions, which consists in the fact that the received input sequence, consisting of several successive words, each of which is a bitwise modulo two sum of an error-correcting cyclic code, a numbering sequence and a phasing sequence, first multiplied by the test polynomial of the error-correcting cyclic code and, as a result of multiplication, the sum of the syndromes of the error-correcting cyclic code, the numbering sequence and the phasing sequence is obtained, then the resulting sum is multiplied by the check polynomial of the numbering sequence and the sum of the syndromes of the error-correcting cyclic code and the phasing sequence is obtained from this sum the phasing sequence syndrome is subtracted and the error-correcting cyclic code syndrome is obtained, which can correspond to one numbering sequence or several numbering sequences each bit in a continuous sequence equal to the number of bits in the codeword of the cyclic error-correcting code is assigned its own label, which is repeated constantly after a period of time corresponding to the transmission of one codeword, therefore, such labels determine the boundaries of the words of the cyclic error-correcting code and the words formed at the junction of two neighboring words of the cyclic error-correcting code, a block of words of the cyclic error-correction code and blocks of words formed at the junction of two adjacent words of the cyclic error-correction code, the threshold value of the number of code words in the synchronizing sequence is equal to the minimum set of code words required to decode the block, and synchronization is carried out according to code words with the number of errors in them no more than the correcting ability of the code words obtained after removing the synchronizing symbols from the input sequence, for each word of the blocks corresponding to its label, synchronized parallel counters but they form a complete set of numbering sequences, the values of these synchronized counters are increased by one in parallel after a period of time corresponding to the transmission of one code word, when the synchronized counters reach their maximum value, the next value of the counters corresponds to their initial value and the cycle time of the synchronized counter is equal to the duration of the numbering sequence, for each synchronized counter of one specific numbering sequence has its own set of match counters for all different labels, the values of each synchronized counter from the full set of numbering sequences for each label are compared by hardware in parallel with the numbering sequence numbers for the corresponding word of the input sequence that is being analyzed at the moment, when coincidence of the word number of the input sequence with the value of the synchronized counter of the numbering sequence The value of their coincidence counter is increased by one, if at the end of the synchronizing sequence in its coincidence counter corresponding to the label of certain words of the input sequence, the value has not reached the threshold value, then only this coincidence counter is reset to its original state, characterized in that, in order to exclude possible of false synchronization of blocks at the end of each numbering sequence, the value of its match counter is compared with the values of all match counters of the remaining labels, if the threshold value is exceeded or equal to the number recorded in this analyzed match counter, and if in any of these counters of labels the value is equal to or greater than the value of the analyzed match counter, or if the value of the analyzed match counter has not reached the threshold value at the end of this numbering sequence, then do not make a decision about the code framing of the input sequence, while resetting only the match counter of this numbering sequence and continuing the operation of determining the correct synchronization of the block, if at the end of each numbering sequence the value of its match counter exceeds or becomes equal to the threshold value and exceeds the value of any match counter of all labels, then a decision is made about the code framing of the input sequence, while resetting all match counters. 2. The method according to claim 1, characterized in that, in order to maximally exclude false synchronization of blocks, after determining the correct synchronization, the counter is started for a period of time corresponding to the duration of the transmission of one block, and if at the end of the count confirmation of the correct synchronization of the block comes, then with further When blocks are transmitted, all possible false synchronization triggers are ignored inside the true blocks of code words, and with each next block transmission, the correct block synchronization is confirmed, if the next confirmation of the correct block synchronization does not arrive, then this means either the end of the message transmission, or, in the worst case, loss of a block, in which case the synchronization algorithm proceeds according to method 1 to search for the correct block synchronization and a new confirmation of the correct block synchronization.