JPH03184439A - Unique word detecting system - Google Patents

Abstract

PURPOSE:To set the number of allowable error bits at the optimum level by controlling the number of allowable error bits for the detection of a unique word corresponding to the quality of a satellite line. CONSTITUTION:An allowable error bit number calculation circuit 10-5 performs the estimation of the error rate of a demodulation signal 102 from a demodulator 1 based on the count result of an error pulse from an error pulse counter circuit 10-4, and calculates the undetection rate of the unique word in the arbitrary number of allowable error bits from the error rate, and calculates the number 113 of allowable error bits from the undetection rate, and sends it to a comparator 8. Thereby, it results that the number 113 of allowable error bits compared with the number 106 of noncoincidence from an adder 5 at the comparator 6 always conforms to the change of the quality of the satellite line, and the number 113 of allowable error bits can be set at the optimum level.

Description

TECHNICAL FIELD The present invention relates to a unique word detection method, and more particularly to a unique word detection method used for receiving burst signals in a satellite communication system using time division multiple access.

Conventional technology When receiving burst signals of a satellite communication system using time division multiple access, a pattern called a unique word signal that has very little correlation with the data signal is inserted at a fixed position in each burst signal, and this unique word signal is By detecting this, the reception timing of the data signal included in the burst signal is obtained.

In the above-mentioned reception timing generation system, it is desirable to have a unique word detector that is reliable and has as few errors as possible.

Furthermore, since the occurrence of bit errors is absolutely unavoidable in satellite communications, the unique word pattern must be detected even if some bit errors occur on the unique word pattern.

Therefore, when detecting a unique word, a permissible number of bit errors is determined in advance, and a unique word is detected when the number of bit errors in a unique word pattern is less than or equal to the permissible number of bit errors.

As the bit error rate on the satellite link increases, the probability that a unique word will not be detected increases as shown in Figure 4, but by increasing the allowable number of bit errors as shown in Figure 5, the probability that a unique word will not be detected increases. The probability of non-detection is reduced.

However, if the allowable number of bit errors is increased, the uniqueness of the unique word is lost, and a unique word detection signal is erroneously output even when the original unique word does not exist, resulting in a unique word error as shown in Figure 5. This will increase the detection probability.

Therefore, the allowable number of bit errors is determined at the intersection of the unique word non-detection probability curve and the unique word false detection probability curve.

Conventionally, in the unique word detection method, as shown in FIG. 3, a received intermediate frequency signal 101 is demodulated by a demodulator 1 and output as a demodulated signal 102.

This demodulated signal 102 is serial-parallel converted by a serial-parallel converter 2, and is converted into a received unique word pattern 103 by a comparator 3.
sent to.

The comparator 3 receives each bit A of the unique word pattern 103 received from the serial/parallel converter 2. -A□, and each bit U of the unique word pattern 104 stored in the unique word pattern storage circuit 4 in advance. ~UNI are compared bit by bit, and the result is output to the adder 5 as a comparison output 105.

In the adder 5, each pip of the comparison output 105 from the comparator 3)
C6-CN-1 is added and the result is the number of mismatches 108
The signal is sent to the comparator 11 as a signal.

The comparator 11 compares the number of mismatches lOB from the adder 5 with a preset allowable number of error bits 114, and if the number of mismatches 108 is less than or equal to the allowable number of error bits 114, a unique word detection pulse 115 is output. .

Here, this allowable error bit number 114 has been determined for a specific line quality, and this value has been used as a fixed value.

In such a conventional unique word detection method, the number of allowable error bits (114) is fixed, so even if the probability of non-detection of a unique word changes due to changes in the quality of the satellite link, the probability of false detection due to random patterns is reduced. Since it is independent of the satellite line quality, it has the disadvantage that the number of allowable error bits is not optimal.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the drawbacks of the conventional methods as described above, and an object of the present invention is to provide a unique word detection method that can optimally set the number of allowable error bits.

Structure of the Invention The unique word detection method according to the present invention is a unique word detection method that demodulates a burst signal of a satellite communication system and detects a unique word from the demodulated signal, and includes a measurement method that measures a line error rate from the demodulated signal. and calculating means for calculating the number of allowable error bits when detecting the unique word from the measurement value of the measuring means, and the number of allowable error bits calculated by the calculating means and the demodulated signal are calculated in advance. It is characterized in that the unique word is detected by comparing the number of error bits counted by comparison with the set unique word.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, one embodiment of the present invention has the same configuration as the conventional example shown in FIG. Identical parts are given the same reference numerals.

Further, the operations of these same parts are also the same as in the conventional example.

The comparator 6 compares the number of mismatches 106 from the adder 5 and the number of allowable error bits 118 from the error middle side determiner No. 10, and if the number of mismatches 106 is less than or equal to the allowable number of error bits 113, it outputs a unique word detection pulse 107. Output.

AND circuit 7 gates unique word detection pulse 107 from comparator 6 at reception control timing 109 from timing generator 9, and outputs the signal as unique word detection pulse 108 to synchronization circuit 8 and timing generator 9. .

That is, since the timing generator 9 predicts the second and subsequent detection timings based on the first unique word detection timing and generates the reception control timing 109, the AND circuit 7 uses unique words other than this reception control timing 109. It functions to eliminate the detection pulse 107.

The synchronization circuit 8 establishes frame synchronization using the unique word detection pulse 108 that has passed through the AND circuit 7, that is, it counts the unique word detection pulse I08 detected at the predicted unique word detection position, and outputs the unique word detection pulse at the predicted unique word detection position. When 108 is detected m consecutive times, it is determined that synchronization has been established. When the synchronization circuit 8 establishes frame synchronization, it outputs a synchronization state signal 110 to the timing generator 9.

The timing generator 9 predicts the second and subsequent detection timings based on the unique word detection pulse 108 that has passed through the AND circuit 7, generates a reception control timing 109, a reception control timing itt, and a reception timing 112, and outputs the reception control timing 109, reception control timing itt, and reception timing 112, respectively. and is output to the synchronization circuit 8 and the error middle side determiner 10.

The error middle side determiner 10 measures the bit error rate of the demodulated signal 102 from the demodulator 1, that is, the line error rate, calculates the number of allowable error bits 113 of the unique word from the line error rate, and outputs it to the comparator 6. do.

FIG. 2 is a block diagram showing the configuration of the error middle side determiner 10 of FIG. 1. In the figure, the error correction circuit 10-l outputs the signal to the demodulator 1 at the reception timing 112 from the timing generator 9.
Errors in the demodulated signal 102 from the demodulated signal 102 are corrected, and the corrected demodulated signal is sent to the data comparison circuit 10-3.

Delay circuit 10-2 delays demodulated signal 102 from demodulator 1 and sends it to data comparison circuit 10-3.

The data comparison circuit 10-3 compares the demodulated signal whose error has been corrected by the error correction circuit 10-1 and the demodulated signal which has been delayed by the delay circuit 10-2, that is, the demodulated signal after error correction and the demodulated signal before error correction. and is compared at the reception timing 112 from the timing generator 9, and the comparison result is sent to the error pulse counting circuit 10-4 as an error pulse.

The error pulse counting circuit 10-4 counts the error pulses from the data comparison circuit 10-3 at the reception timing 112 from the timing generator 9, and outputs the counting result to the allowable error bit number calculation circuit 10-5.

The allowable error bit number calculation circuit 10-5 calculates the number of error pulses from the demodulator 1 based on the error pulse counting result from the error pulse counting circuit 10-4.
Estimate the error rate of the demodulated signal 102 from the error rate, calculate the unique word non-detection rate for any allowable number of error bits from the error rate, calculate the allowable number of error bits 113 from the non-detection rate, and use the comparator. Send on 6.

That is, when the bit error rate on the line is Pe, the bit length of the unique word pattern is N, and the number of allowable error bits is ε, the unique word non-detection probability Pm is expressed as follows.

On the other hand, the false detection probability Pf of a unique word due to the random signal of the demodulated signal 102 from the demodulator 1 is P f −(
1/2) NΣ(NC1)4m(+ is represented.

The allowable error bit number calculation circuit 10-5 calculates P in the above equation.
The allowable error bit number ε is calculated so that m-Pf,
The calculation result is output as the number of allowable error bits 113.

Therefore, the number of allowable error bits 113, which is compared with the number of discrepancies lOB from the adder 5 in the comparator 6, always corresponds to changes in the satellite channel quality, and the number of allowable error beats 113 can be optimally set.

In this way, the error rate of the demodulated signal 102 from the demodulator 1 is measured, and the allowable error bit number U3 is calculated from the error rate,
The number of allowable error bits ill and the number of mismatches from the adder 5 1
06 to detect a unique word, the number of allowable error bits can always be optimally set.

As described in detail, according to the present invention, by controlling the number of permissible error bits for unique word detection according to the quality of the satellite line, the number of permissible error bits can be optimally set. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the error middle side limiter of FIG. 1,
Fig. 3 is a block diagram showing the configuration of a conventional example, Fig. 4 is a diagram showing the relationship between the bit error rate of the satellite line and the probability of non-detection of unique words, and Fig. 5 is a diagram showing the relationship between the number of allowable error bits and the probability of non-detection of unique words. FIG. 3 is a diagram showing the relationship between detection probability and false detection probability. Explanation of codes of main parts 1... Demodulator 5... Adder 6... Comparator 7... AND circuit 8... Synchronization Circuit 9... Timing generator 10... Error middle side regulator 0-1... Error correction circuit 0-2... Delay circuit 0-3... ...Data comparison circuit

Claims (1)

[Claims] (1) A unique word detection method that demodulates a burst signal of a satellite communication system and detects a unique word from the demodulated signal, comprising a measuring means for measuring a line error rate from the demodulated signal, and a measurement value of the measuring means. calculating means for calculating the allowable number of error bits when detecting the unique word from the above, and comparing the allowable error bit number calculated by the calculating means with the demodulated signal and the unique word set in advance. The unique word detection method is characterized in that the unique word is detected by comparing the number of error bits counted by the method.