JPH0697928A - Synchronous word detecting circuit - Google Patents

Abstract

PURPOSE:To reduce synchronous word non-detection probability by detecting synchronous words of two continuous burst signals through a correlator, and using a second synchronous word detection pulse, when the synchronous word of a first burst signal is not detected. CONSTITUTION:The respective synchronous words of two continuous burst signals from an elastic buffer 31 are detected simultaneously by correction detectors 33, 34 for taking a correlation to a reference synchronous pattern. When the synchronous word of the first burst signal is not detected, an inhibiting circuit 35 becomes an inhibited state, a synchronous word detection pulse of a second burst signal by the correlator 34 from adder 36 is used a first receiving timing is generated, and read-out of data of the first burst signal is executed. According to this constitution, the synchronous word non-detection probability is reduced, and loss probability of the data becomes small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to time division multiple access (TD).
D) A sync word detection circuit used for receiving a burst signal of a communication system.

[0002]

2. Description of the Related Art When a burst signal of the TDD communication system is demodulated and received, a pattern called a sync word having a very low correlation with a data signal is inserted at a fixed position of each burst signal, and the sync word position is inserted. Is detected to identify the data position in the burst signal and generate the reception timing such as the decoding timing of the encoded data and the extraction timing of the control signal. Therefore, if the sync word is not detected or erroneously detected, data loss occurs and the line quality significantly deteriorates.

In the conventional sync word detecting circuit, since the sync word position is correctly detected even when the sync word including the bit error is received, the allowable error bit number (ε) is set in advance and the received sync word is transmitted. If the number of mismatches with the sync word is ε bits or less, the sync word is detected by using the correlation detector which is supposed to be correctly detected.

FIG. 3 shows an example of the configuration of a conventional sync word detecting circuit to which a correlation detector is applied. The received data 101 is input to the shift register 11, the number of mismatches with the reference synchronization word pattern 102 held in the register 12 is calculated by the mismatch number addition circuit 13, and the number of mismatches is calculated by the comparator 14 as the allowable error bit number (ε ) A detection pulse is output at a bit position of 103 or less. After that, the gate 15 outputs a logical product with the aperture window 104 as a sync word detection pulse 105.

According to the present circuit, even if a bit error of up to ε bit occurs in the received sync word, the sync word can be correctly detected, and ε has a low sync word non-detection rate and a low false detection rate. It is possible to reduce the data loss probability by optimizing the value. Studies on the optimization of ε have been made in the field of satellite communication (for example, W. Schrem
pp and T. Sekimoto: "Unique word detection in digital
burst communications ", IEEE Trans.on Commun.Techno
l.COM-16, No.4, pp.597-605 (Aug.1968)). Based on these studies, the error of the sync word of 16 bits and the humming distance of 6 in a thermal noise environment with a line error rate of 0.01
The false detection rate characteristics are shown in FIG. Both the non-detection rate and the false positive rate are low, and ε is 3, and the sync word non-false positive rate is 2 × 1.
0 ^-5.

Further, when the Doppler frequency is lower than the signal transmission speed and the signal propagation path is short, the time-varying component of the reception clock does not exceed one symbol length within one frame, and the continuity of the reception clock is Since it is maintained, the sync word position can be specified by the free-running counter after the sync word is detected once. That is, when the transmission timing of the transmitting station is not changed, there is no difference in the data position detected by the free-running frame and the sync word.

[0007]

However, in the conventional circuit, when the sync word is not detected by the correlation detector, the data received as the sync word non-detection is discarded, so that the data loss due to the non-detection of the sync word. There was a problem that the probability deteriorated significantly. If you try to prevent this by using the above-mentioned free-running counter, if the synchronization word of the burst signal in the frame whose transmission timing has been changed cannot be detected at the transmitting station, the synchronization word output by the free-running counter. Position pulses are not applied correctly, again resulting in data loss. Since the transmission timing is controlled for each symbol, the probability that the sync word position can be correctly detected after the non-detection of the sync word is 1/3, and the data loss occurs with the probability of 2/3 when the transmission timing is changed.

In the case of erroneous detection of a sync word, a detection pulse is output but its position is erroneous, resulting in data loss similar to non-detection, but the erroneous detection rate largely depends on the pattern of the sync word. Therefore, generally, the optimum pattern is calculated and given by computer simulation or the like.
Therefore, the non-detection rate of the sync word can be improved by the sync word detection method.

The present invention has been made in view of the above,
The purpose is to reduce the probability of non-detection of synchronization words,
It is an object of the present invention to provide a sync word detection circuit that can reduce the probability of data loss.

[0010]

To achieve the above object, a sync word detecting circuit of the present invention detects a sync word by demodulating a burst signal of a time division multiple access communication system and detecting the sync word from the demodulated signal. A circuit for accumulating the demodulated signal for two burst signals; and a correlation between a synchronization word included in the demodulation signal of each burst signal of the two accumulated burst signals and a reference synchronization word. And a correlation detector for detecting, and when the sync word of the first burst signal cannot be detected, the sync word position of the first burst signal is estimated by the sync word detection pulse of the second burst signal. The gist is to detect the synchronization word and read the data of the first burst signal.

[0011]

In the synchronizing word detecting circuit of the present invention, the first detecting operation is performed by simultaneously detecting the synchronizing words of two continuous burst signals.
Even if the sync word of the 1st burst signal is not detected, the 1st reception timing is generated using the 2nd sync word detection pulse, and the data of the 1st burst signal is read. .

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a sync word detecting circuit according to an embodiment of the present invention. In the figure, received data 101 for two burst signals from a demodulator (not shown) is input to the elastic buffer 31,
Two correlation detectors 33, 34 separated by the burst length
The sync words of the two burst signals are respectively detected by. Number of allowable error bits (ε) for each of the two detectors
103 and an aperture window 104 for detecting a sync word are set in advance. When the synchronization word of the first burst signal is detected by the correlation detector 34, the detection pulse is used to read the first burst signal. On the other hand, the first
When the sync word of the th burst signal is not detected by the correlation detector 34, the first burst signal is read using the second sync word detection pulse, and then the second burst signal is read. In order to perform such an operation, the sync word detecting circuit of this embodiment does not use the output pulse of the correlation detector 34 to ignore the detection pulse of the correlation detector 33, or the output pulse of the two correlation detectors. Of the sync word detection pulse 10 from the adder circuit 36 and the elastic buffer 31
Read control circuit 3 for outputting read data 304 according to
2 is provided.

When the transmission timing of the transmitting station is changed by applying the synchronization word detection circuit of this configuration, the error in the synchronization word detection position continues when the first burst signal with no symbol shift is not detected. The data loss probability is 2 × (1/3 × 1/2) because it is only when the sync word detection position of the second burst signal is deviated by ± 1 symbol.
= 1/3.

When the synchronous word non-detection rate of the synchronous word detection circuit of the present invention is Ppm, the false detection rate is Pfm, the synchronous word non-detection rate in the correlation detector is Pm, and the false detection rate is Pf, respectively, Can be derived to. First, since the non-detection rate is the probability of not being detected by any of the two independent correlation detectors, it is given by the product of the non-detection probabilities of each detector.

[0016]

## EQU00001 ## Ppm = Pm.times.Pm (1) On the other hand, the false detection rate is a value obtained by subtracting from 1 the probability of correct detection by both of the two independent correlation detectors.

[0017]

[Number 2] Pfm = 1- (1-Pf) 2 = 2 × Pf-Pf 2 ... (2) Equation (1), the synchronization word in the thermal noise environment of channel error rate 0.01 calculated from (2) FIG. 2 shows the non-detection / erroneous detection probability characteristics of a synchronization word having a length of 16 bits and a Hamming distance of 6. The number of permissible error bits that reduces both the non-detection rate and the false detection rate is 2, and the non-detection / erroneous detection rate is 3 × 10 ⁻⁷ , which is one digit or more lower than that of the conventional circuit.

Since the data loss probability when the transmission timing of the transmitting station is changed is 1/3, the data loss probability at the time of changing the transmission timing can be reduced by 50% as compared with the conventional circuit.

[0019]

As described above, according to the present invention,
Even if the sync word of the first burst signal is not detected by detecting the sync words of two consecutive burst signals at the same time, the first reception timing is determined by using the second sync word detection pulse. Since the first burst signal is generated and the data of the first burst signal is read, the received burst signal is not discarded and therefore data loss does not occur.
Further, even if the sync word is not detected in the frame in which the transmission timing of the transmitting station is changed, the sync word position is estimated from the burst signal of the next frame, so that the probability of data loss can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sync word detection circuit according to an embodiment of the present invention.

FIG. 2 is a graph showing a sync word non-erroneous detection rate characteristic of the sync word detection circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional sync word detection circuit.

FIG. 4 is a schematic diagram showing a conventional sync word detection circuit shown in FIG.
It is a graph which shows a false detection rate characteristic.

[Explanation of symbols]

 11 shift register 12 register 13 disagreement number addition circuit 14 comparator 31 elastic buffer 32 read control circuit 33, 34 correlation detector 35 prohibition circuit 36 addition circuit

Claims (1)

[Claims] 1. A sync word detecting circuit for demodulating a burst signal of a time division multiple access communication system and detecting a sync word from the demodulated signal, and an accumulating means for accumulating the demodulated signal for two burst signals. And a correlation detector that detects a correlation between a synchronization word included in a demodulated signal of each burst signal of the two accumulated burst signals and a reference synchronization word, and the synchronization word of the first burst signal is When it cannot be detected, the sync word position of the first burst signal is estimated by the sync word detection pulse of the second burst signal to detect the sync word, and the data of the first burst signal is read. Sync word detection circuit.