JPS609241A - Synchronizing protection system - Google Patents

Abstract

PURPOSE:To realize the optimum forward protection capacity for a PCM communication device by changing the set value of a discordance number counter in accordance with the reception signal level. CONSTITUTION:The signal transmitted from a transmission line is applied to a synchronism detection circuit 3 via a demodulating circuit 2 in the form of the data signal and bit clock. The synchronizing signal is extracted out of each frame. The signal level value obtained from a detecting circuit 13 is turned into the n-bit numerical value after sampling/holding and A/D conversion, and an ROM16 is addressed. The optimum value N2 to the code error factor corresponding to the reception signal level is written to the ROM16. As a result, the set count value N2 of a discordance number counter 7 varies automatically in response to the change of the output signal level value of the circuit 13. Thus the forward protection is always secured in an optimum state even though the reception signal level varies in terms of time.

Description

TECHNICAL FIELD The present invention relates to a protection system in a frame synchronization circuit of a PCM communication device.

BACKGROUND ART In the field of PCM communication, frames are often sent periodically and repeatedly. Therefore, when the synchronization pulse arrangement is sequential, the frame synchronization pulses detected from this synchronization pattern are monitored, and when the synchronization breaks down, synchronization is pulled in by noting, and the synchronization signal is corrected. It has gained. However, a synchronization protection circuit is provided so as not to confuse intensive transmission line code errors with synchronization part failures. Normally, a synchronization protection circuit has a forward protection ability that detects synchronization pulses that are detected intensively for a certain period of time and goes into a hunting state when the synchronization pulses deviate. It also has a backward protection capability that prevents incorrect synchronization decisions.

The forward protection mentioned above compares the synchronization signal detected from the synchronization pattern and the frame synchronization signal counted by the pit clock with a frame counter, and counts the mismatched pulses generated by this with a counter, and sets the count to a specific value. When the value exceeds this value, it is determined that synchronization has been lost. The forward protection ability is determined by the size of this set count value.

In a communication system with little jitter, the set count value of a counter that counts the number of mismatched pulses may generally be relatively small. However, this is only in a steady state, and in systems such as wireless systems where the signal propagation condition temporarily deteriorates depending on the spatial condition, there are many transmission line code errors, and people often get caught in a hunting state. Put it away. In order to prevent this, if the set count value is set too high, there is a drawback that recovery in the event of loss of synchronization is delayed.

DISCLOSURE OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a synchronization protection system that has an optimal forward protection capability even in a communication system where transmission line code errors temporarily vary significantly. There is a particular thing.

The synchronization protection system according to the present invention is applied to a communication system in which encoded data is transmitted frame by frame, and each frame includes a synchronization signal formed in the same pattern and is repeatedly transmitted.

The synchronization protection system according to the present invention detects a synchronization signal by receiving an encoded data signal, monitors the mismatch between the synchronization signal pattern and a pre-prepared pattern for each frame, and calculates the number of mismatches. When a preset value set in advance is reached, a non-taking pulse is generated, and when this hunting pulse is given, the above-mentioned received encoded data signal is shifted in 1-bit units to perform synchronization pull-in. The present invention is characterized in that means is provided for automatically changing the set count value of a mismatch number counter for counting synchronization mismatch pulses in accordance with the received signal level of the synchronization mismatch pulse. In general, the nature of communication systems.

The situation differs depending on the carrier wave modulation method, receiver installation conditions, etc., but if the received signal level is thick, there will be few transmission line code errors, and conversely, if the received signal level is low, there will be many transmission line code errors. Therefore, in the configuration of the present invention, the transmission path code error rate for the received signal level of the encoded data signal is set in advance based on the above communication system characteristic 1 condition, etc., and the set transmission path code error rate is set at the received signal level. By referring accordingly, an optimal setting count value that prevents non-counting due to code errors is calculated, and this is supplied as a preset value to be compared with the number of mismatches.

With the above-described configuration, the synchronization protection system of the present invention can always have optimal forward protection capability even when there are fluctuations in signal propagation conditions.

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment to which the present invention is applied when a contention counter method is used as a synchronization protection system. A signal entering the receiver from the transmission path is amplified by a preamplifier 1, and a demodulation circuit 2 obtains a PCM encoded data signal and a pit clock from the signal.

Then, the data signal and pit clock enter the synchronization detection circuit 3, and a detected synchronization signal is extracted from the synchronization pattern within each frame. The detection synchronization signal is sent to the coincidence detection circuit 4. When the synchronization signal that is guided to the mismatch detection circuit 5 and is outputted from the frame counter 12 matches or does not match, a match pulse is generated from the above-mentioned detection circuits 4 and 5 according to each.

A mismatch pulse is output. The coincidence pulse and the mismatch pulse are respectively detected by the coincidence number counter 6. When the mismatch counter 7 counts and reaches a preset count value Nr, N2, the flip-flop 9 is reset and set. When the output Q of the flip-flop 9 is set, each time a mismatch pulse is output from the mismatch detection circuit 5, a non-tinging pulse is output from the AND circuit 10, and a pit clock pulse that passes through the clock gate 11 is generated. It attempts to prevent this and shift the phase by one pit to achieve synchronization. Synchronization signal is clock gate 11
The frame counter 12 counts the pulse trains passing through the frame counter 12. Counter 6.7 reset is OR
This is done via circuit 8 for each output of the counter and for each hunting pulse. Mismatch number counter 7
Set count value N2. The synchronous protection capability of forward protection and backward protection is determined by the size of the set count value N1 of the coincidence number counter 6.

However, as mentioned in the background art section, in communication systems where the steady propagation state is often disturbed, where the signal propagation state varies greatly over time depending on the spatial condition, the set count value N2 is kept constant. It is extremely inappropriate to leave it as such. This is because there is a difference between the received signal level of the transmission path and the bit error rate, which depends on the modulation method of the carrier wave or the installation conditions of the receiver, but there is a general relationship between Because of this relationship, if the signal propagation state of the communication system changes due to disturbance phenomena, the bit error rate will also change. Therefore, even if the set count value N2 of the discrepancy counter 7 is determined assuming a steady-state bit error rate as forward protection, when the received signal level decreases, the bit error rate becomes significantly higher than the steady-state value, and becomes extremely It often enters a hunting state and its forward protection ability is reduced. In the system according to the present invention, the above-described synchronization protection circuit is improved, and the signal level detection circuit 13. Sample and hold circuit 14. AD converter 1
5. Read-only memory (hereinafter referred to as ROM) 16.
A latch circuit 17 is provided, and the set count value N2 of the mismatch number counter is determined and preset by the output of the latch circuit 17. This means that the set count value N2 of the mismatch number counter 7 is not fixed but is variable depending on the received signal level. This operation will be explained below. First, the signal level value obtained by the signal level detection circuit 13 is sampled and held and AD converted into an n-bit digital value, and the ROM 16 is addressed with this value. The ROM 16 stores the set count value N2 of the mismatch number counter 7, which is optimal for the bit error rate corresponding to the received signal level shown in FIG. Therefore, if the signal level value of the signal level detector 13 changes, the set count value N2 of the mismatch number counter 7 will automatically change. As a result, even if the received signal level fluctuates over time, forward protection is always performed in an optimal state. The numerical value written to each address in the ROM 16 differs depending on the modulation method, receiver installation conditions, etc., as described above, but once determined empirically, it is sufficient. Further, since the determination of the set count value N2 does not need to be very precise, the AD converter 15. ROM16
etc., the number of bits is small.

As shown in this embodiment, by adding an extremely simple circuit to the conventional synchronous protection circuit, it is possible to obtain a system that always performs forward protection optimally. Further, although the embodiment is an example in which the present invention is applied to a competition type synchronization protection circuit, the present invention can be applied to any synchronization protection system as long as it includes a circuit for counting the number of discrepancies using a discrepancy counter.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment in which the present invention is applied to a competitive synchronization protection system, and FIG. 2 is a diagram showing the general relationship between received signal level and bit error rate. DESCRIPTION OF SYMBOLS 1... Preamplifier, 2... Demodulation circuit, 3... Synchronization detection circuit, 4... - scattering output circuit, 5... Mismatch detection circuit, 6... Match number counter, 7 . . . Mismatch number counter, 8 . . OR circuit, 9 . . . Flip-flop, 10 , 11 .
・Sample hold circuit, 15...AD converter, 16...ROM. 17...Latch circuit.

Claims (1)

[Claims] In a communication system in which an encoded data signal is transmitted frame by frame, and each frame includes a synchronization signal formed in the same pattern and is repeatedly transmitted, the encoded data signal is received. By this, the synchronization signal is detected, the mismatch between the synchronization signal pattern and a pre-prepared pattern is monitored for each frame, and a hunting pulse is generated when the number of mismatches reaches a preset value. The system performs synchronization by shifting the received coded data signal in units of 1 bit by applying this hunting pulse, and the system performs synchronization by shifting the received coded data signal bit by bit. Optimum set count value to prevent counting due to code errors by setting the transmission line code error rate in advance according to the characteristics, conditions, etc. of the communication system, and referring to the set transmission line code error rate according to the received signal level. A synchronization protection system characterized in that the synchronization protection system calculates and supplies this as a preset value to be compared with the number of discrepancies.