SU1310895A1 - Device for checking multichannel magnetic tape recorder - Google Patents

Abstract

The invention relates to the accumulation of information and can reduce the errors in the control of the device. When checking the correctness of the detection and correction of errors, the trailing edge of the marker pulse switches the pulse counter 16, the state of which is decoded by the decoder 19, affecting the gating unit 12. At the end of the marker pulse, blocking is removed from the counters 14 and 15 pulses. The pulse counter 14 starts counting the clock pulses and, after a predetermined number of cycles, generates a signal that triggers trigger 8. The counter pulse signal 14 arriving at its blocking input stops the clock pulse count. After switching, trigger 18 enables the counter 15 pulses to count the clock pulses. Through the number of ticks equal to twice the specified number of ticks, the counter 15 generates a signal that flips the trigger 18 to its initial state, providing the gating of the signals of the decoder 19 by the gating unit 12. The pulses of the gating unit 12 are fed to the adders 8 modulo two, acting through the register 3 on the multichannel magnetic recording apparatus 4. 1 il. I (L oo with SP

Description

The invention relates to the accumulation of information, namely, devices for controlling a multichannel magnetic recording apparatus.

The aim of the invention is to reduce the error of control of a multichannel magnetic recording apparatus.

The drawing shows one of the possible variants of the proposed device for controlling a multichannel magnetic recording apparatus.

The device contains a generator 1, connected by an output to the input of test driver 2, a register 3, the outputs of which are connected through a multichannel magnetic recording device 4 to the inputs of a channel-5 decoding unit, a driver 6 of an aggregate error signal, connected by an output to the input of an error counter 7, and adders 8 but modulo two.

The device also contains a channel-coding unit 9 whose outputs are connected to the first inputs of adders 8 module two and to a signal input of a register 3 connected by other signal inputs to outputs of modulators 8 modulo two, a parity signal generator 10 connected by inputs to the signal outputs of driver 2 test, the first driver 11 sync pulses connected to the output of the clock signal of the driver 2 tests, block 12, connected by the outputs to the second inputs of the adders 8 modulo two, the inverter 13 connected by the output with the control input of the register 3, the first, second and third counters 14-16 pulses, the error-correcting coding unit 17, the trigger 18, the decoder 19, the second driver of the sync pulses 20, the marker decoding unit 21, the time alignment unit 22, the analyzer 23 states of the remainder of the cyclic control code, the correction signal generator 24, the erroneous bits correction unit 25, the indication signals generator 26 and the indicator 27. The outputs of the first generator 11 sync pulses are connected to the clock input of the 9 p block channel coding, to the input of inverter 13 to the count input of the first and third counters .vtorogo 14-16 pulses for adjusting inputs of the first and second counters 14 and 15 are controlled by pulses and l yushim input unit 17 error-correcting coding. The error-correcting coding unit 17 is connected by signal inputs to the signal outputs of the test former 2 and the output of the parity signal generator 10. The output of the first pulse counter 14 is connected to its blocking input and is connected to the first input of the trigger 18. The trigger 18 is connected by the second input to the output of the second counter0

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ka 15 pulses. The trigger 18 is also connected via an output to the blocking input of the second pulse counter 15 and to the gate input of the gate unit 12, the signal inputs of which are connected via the decoder 19 to the outputs of the third pulse counter 16 pulses. The outputs of the channel-by-channel decoding unit 5 are connected to the signal inputs of the second shaper 20 clock pulses and the time alignment unit 22, to the first group of control inputs of the analyzer 23 of the state of the residual cyclic control code, and to the inputs of the marker decoding unit 21. The marker decryption unit 21 is connected by an output to the control input of the second synchronizer generator 20 and connected to the second group of control inputs of the analyzer 23 for the remainder of the cyclic control code and to the first group of control inputs of the time alignment unit 22. The outputs of the time alignment unit 22 are connected to the input of the parity signal of the correction signal generator 24 and to the signal inputs of the error bit correcting unit 25 connected by the outputs to the signal inputs of the total 6 signal of the error. The outputs of the second synchronizer generator 20 are connected to the second group of control inputs of time alignment unit 22, with the clock inputs of the erroneous bits correction unit 25 and the total error signal generator 6, and with the control inputs of the correction signal generator 24 connected by the outputs to the correction signal inputs of the correction unit 25 of the alarm bits and the signal inputs connected to the outputs of the analyzer 23 of the state of the remainder of the cyclic control code connected via the signal generator 26 indication to the inputs of the indicator 27.

The control of a multichannel magnetic recording apparatus by means of the device proposed is as follows.

The master oscillator 1 acts on the test driver 2, generating test signals and the accompanying clock signal supplied to the error-correcting coding unit 17, on the parity signal generator 10 and on the first driver 11 clock pulses. The first driver 11 of the clock pulses directly on the noise-resistant coding unit 17 and the channel-9 coding unit 9, and through the inverter 13 on the register 3. The error-correcting coding unit 17, the parity signal generator 10 and the first synchronizer driver 11 separate the signal to be recorded into blocks, recoding and padding with control residues and markers. Channel-channel coding unit 9 produces channel-by-channel coding of signals of noise-resistant coding unit 17 in accordance with the selected type of record. The signals of the channel-9 coding unit 9 through the adders 8 modulo two and the register 3 affect the multichannel magnetic tape apparatus 4, in which they are recorded on the magnetic tape. The reproduced signals are fed from the multichannel magnetic recording apparatus 4 to the channel decoding unit 5, the signals of which are sent to the marker decoding unit 21, the time alignment unit 22, the cyclic control code balance analyzer 23 and the second synchro pulser 20. The marker decoding unit 21 acts on the second synchronization pulse generator 20, the time alignment block 22 and the cyclic control code balance state analyzer 23, the time alignment block 22 on the correction signal generator 24, and the error state analyzer 23 cyclic control code on shaper 24 of the correction signal, shaper 24 of the correction signal on block 25 for correction of erroneous bits, and the second driver 20 clock pulses on block 22 of time alignment , To the analyzer 23 of the state of the remainder of the cyclic control code, to the correction signal generator 24, and to the error bit correction block 25. Channel decoding unit 5, marker decoding unit 21, time alignment unit 22, cyclic control code balance state analyzer 23, correction signal generator 24, error bit correcting unit 25, and second clock generator 20, perform channel-by-channel decoding of the reproduced signals, highlighting markers, temporal alignment by columns, analysis of the state of the remainder of the cyclic control code, generation of a correction signal and error correction, if their number is not more than one in the column. In this case, the analyzer 23 of the state of the cyclic monitoring code acts through the shaper 26 of the indication signals on the indicator 17, and the error bit correcting unit 25 and the second shaper 20 of the clock pulses through the shaper 6 of the total error signal on the counter 7 errors.

When checking the correctness of the detection and correction of errors, the trailing edge of the marker pulse switches the third pulse counter 16, the state of which is decrypted by the decoder 19 affecting the gating unit 12. At the end of the marker pulse is removed

blocking from the first and second counters 14 and 15 pulses. In this case, the first pulse counter 14 starts counting the clock pulses and, after a predetermined number of cycles, generates a signal switching the trigger 18. The signal of the first pulse counter 14 arriving at its blocking input stops counting the clock pulses, after switching the trigger 18 resolves to the second

Q counter 15 pulses counting clock pulses. Through a number of ticks equal to twice the value of a given number of ticks, the second counter 15 generates a signal that flips trigger 18 to its initial state, gating the signals of defender 19 by gating unit 12. The pulses of the gating unit 12 are fed to the adders 8 modulo two, acting through the register 3 on the multichannel magnetic recording apparatus 4.

Claims (1)

Invention Formula five A device for controlling a multichannel magnetic recording apparatus, comprising a master oscillator connected by an output to the input of the test driver, a register whose outputs are connected via a multichannel magnetic recording apparatus to the inputs of a channel-decoding unit, A total error signal generator connected by an output to an input of an error counter, and modulo-two adders, characterized in that, in order to reduce the control error, a channel-coding unit is entered into it, the outputs of which are connected to the first inputs of modulators two and to the signal input of a register connected by other signal inputs to the outputs of modulo-two adders, a parity signal generator connected by inputs to the signal outputs of the test driver, the first driver of a sync pulse ow connected by the input to the output of the sync signal of the test driver, gating unit connected by outputs to the second inputs of the sum of 5 moduli two, the inverter connected to the control input of the register, the first, second and third impulse counters, block of error-correcting coding, trigger, decyfender, second clock generator, decoding unit 0 markers, time alignment unit, cyclic control code balance state analyzer, correction signal conditioner, security bits correction unit, indication signal conditioner and indicator, with the outputs of the first sync pulse generator connected to the channel input of the channel-channel coding unit, to the inverter input, to the counting inputs first, second and third score5 pulse inputs, to the installation inputs of the first and second pulse counters and to the control inputs of the noise-resistant coding unit connected by the signal inputs to the signal outputs of the test driver and the output of the parity signal generator, the output of the first pulse counter is connected to its blocking input and connected to the first trigger input connected by a second input to the output of the second pulse counter and connected by an output to the blocking input of the second counter and to the gate input of the gating unit The signal inputs of which are connected via the decoder to the outputs of the third pulse counter, the outputs of the channel-based decoding unit are connected to the signal inputs of the second clock generator and the time alignment unit, to the first group of control inputs of the analyzer of the state of the remainder of the cyclic control code, and to the inputs of the decryption block of the markers connected an output with a control input of the second sync pulse generator and connected by other outputs to the second group of control inputs of the state analyzer of the remainder of the cyclic control code and to the first group of control inputs of the time alignment unit, the outputs of which are connected to the input of the parity signal of the correction signal generator and the signal inputs of the error bit correcting unit connected to the signal outputs inputs of the totalizer error signal generator, and the outputs of the second sync pulse generator are connected to the second group of control inputs of the time block equals, with the synchronization inputs of the error bit correcting unit and the total error signal generator, and with the control inputs of the correction signal generator, connected by the outputs to the error bit correction correction signal inputs and connected to the signal inputs of the cyclic control code balance analyzer outputs, connected through the driver of the indication signals with the indicator inputs.