SU1282212A1 - Device for checking multichannel magnetic tape recorder - Google Patents

Abstract

The invention relates to instrumentation engineering and reduces the error in control. The device contains a master oscillator 1, the device 2 magnetic recording, shaper 3 codes, registers 4,7,14 and 15, shaper 5 sync signals, blocks 6 and 12 adders, block 8 error recording, key elements 9 and 10, the element OR 11, the element Both 16 and block 13 controlled inverters. The introduction of new elements and the formation of new connections between the elements of the device allows one to control the entire area of the magnetic carrier using a pseudo-random control signal. 2 Il.

Description

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The invention relates to instrumentation, namely, to devices for xstrolen multichannel magnetic recording apparatus.

The purpose of the invention is to reduce the control error due to the control over the entire area of the magnetic carrier when using a pseudo-random control signal.

FIG. 1 shows one of the possible variants of the device for controlling a multi-channel magnetic recording apparatus; in fig. 2 - diagrams, according to the principle of formulations and a pseudo-random sequence in rows.

A device for controlling a multichannel magnetic recording apparatus contains a generator 1, which is connected by an output to the interconnected synchronizing input of magnetic recording apparatus 2 and the input of the code generator 3 connected by the outputs through magnetic recording apparatus 2 to information inputs of the buffer register 4, subkey sync input to interconnected sync output of magnetic recording device 2 and input generate 5 sync signals and codes to the first inputs of the first block 6 s mmatorov modulo two outputs connected to the inputs of the first register 7 is connected to a control input to the corresponding output of the 5 clock signals and outputs to the recording unit 8 inputs the error, the first and second br klyuchevr elements 9 and 10 and an OR gate. eleven.

In addition, the device for controlling a multi-channel magnetic recording device contains the second unit 12 modulo-two adders, the unit 13 controlled inverters, the second and third registers 14 and 15, and the AND 16 element connected by the first input through the IPI element 11 to the outputs of the second block 12 adders Motulu two, the second input to the corresponding output of the driver 5 sync signals and the output to the setup input of the first register 7 connected by outputs to the first inputs of the unit 13 controlled inverters connected via codes to the inputs of the second register 14 and the second entrances to soy

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interconnected outputs buffer--nm register 4 and first inputs BTOpoi o block 12 modulo-two adders, connected by pin x x second inputs to outputs from the first to the last-last digit of the third register 15, connected by a synchronization input to the synchronous input connected to the third input register 14 and the corresponding output of the synchronizer 5 sync signals and the outputs of the last and the last and last bits to the inputs of the second key element 10 connected by the output to the additional second input of the second block 12 sum- modulators two, and the second register 14 is connected by the outputs FROM the first to the penultimate bits to the second inputs of the first block 6 modulo-two adders and the outputs of the last and penultimate bits to the inputs of the first key element 9 connected by the output of the first one block 6 modulo adders.

The device works as follows.

Formed. 3 codes generates a test signal in the form of a pseudo-random sequence with a frequency equal to the speed; I and a; information on the magnetic recording apparatus 2, and after transforming into a parallel code is inputted into the magnetic recording apparatus 2 by the signals from generator 1.

In this case (at the top of FIG. 2), the structure of each recorded column is a new, shifted relative to the previous column by one measure, a fragment of a pseudo-random sequence. A pseudo-random sequence is recorded in a track, shifted} One cycle relative to the sequence recorded on the adjacent track. As a result, the proposed control field 1x dan. To the tape recorded on a magnetic tape is the placement of a pseudo-random test signal along the magnetic tape ( i.e., on the line) and across it (i.e., in the column), which brings the test conditions of the multichannel magnetic recording equipment to the real ones with a close approach.

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The reproducible column with the help of its sync pulse is written (on the front of the sync pulse of reproduction) into the buffer register 4.

The playback clock also arrives at the input of the 5 sync driver.

The imaging unit 5 synchronizes in time the operation of all the nodes and blocks of the measuring part of the device and forms at its four outputs for the period of following the clock pulses of reproduction through one synchronization pulse, which is short in duration. Moreover, the pulses at the four outputs of the imager are shifted relative to each other and relative to the front of the playback clock by an amount not less than the duration of the pulses.

The purpose of the synchronization pulses is as follows.

The first synchronization pulse writes (after writing the reproduced column to the buffer register 4) the signals of the allotted errors into the register 7.

The second synchronization pulse interrogates the element AND 16 and, in the presence of a signal at the second input of this element, deletes (clears) the contents of the register 7.

The third synchronization pulse records the error signals in the error recording block 8.

The fourth synchronization pulse overwrites the contents of the buffer register 4 into the third register 15 and into the second register 14. In this case, the register 14 information of the buffer register 4 can be recorded using inverted controlled inverters of the unit 13 of controlled inverters.

Let the previous column stored in the second register 14 have no errors.

The element-by-element comparison of the reproduced column with the previous one is performed using modulo adders of two blocks 6 and shifted by one bit (below in Fig. 2).

In order to compare two adjacent columns with a shift to one bit, it is necessary to know the value of the additional bit, which is not in the previous column stored by register 14. To regenerate the value of the additional (previous)

 the fragment of the sequence stored by the reference register of bits is the key element 9 - with modulator two modulator, which forms the value of the additional bit on the basis of the known law of formation of a pseudo-random sequence in the code generator 3.

So, the value of the first bit of the buffer register 4 is compared with the output signal of the key element 9 (at the bottom of Fig. 2), the value of the second bit of the buffer register 4 with the value of the first bit of register 14, etc. until the last (seventh) bit of the buffer register 4 is compared with the value of the penultimate (sixth) bit of register 14.

If this column is reproduced correctly, then the error signals at the outputs of the modulo-two adders have no block 6 and the register O at the time of the arrival of the first synchronization pulse is written in all bits, which means that they are not in them. Error signals (symbols 1) at the outputs of the bits of register 7 are absent, therefore, there are no error signals and at the control inputs of the inverters of the block 13 5 which in this case the output signals of the buffer register 4 np are inverted.

A quarter pulse of synchronization information from buffer register 4, i.e. This error-free column, without change, is overwritten in register 14, and also entered in register 15.

The next played column is written with its sync pulse into the buffer register 4.

Let there be an error in this column in the fifth channel (in the fifth level of the buffer register 4). By comparing this column with the previous faultless column stored in register 14, a signal is generated at the output of the fifth adder of block 6 (high level of logic 1). errors, which is recorded by the first synchronization pulse in the fifth register bit 7.

The third synchronization pulse records the output signal (error) of the nth register bit 7

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to the corresponding bit of the error register.

The output signal of the fifth bit of the register 7 is also fed to the control input of the fifth controlled inverter of block 13. With this signal present, the fifth inverter of the block 13 inverts the output signal of the fifth bit of the buffer register 4.

With the fourth synchronization pulse, information from the buffer register 4 is overwritten into register 15 and into register 14. Moreover, the erroneous value of the fifth bit of the buffer register 4 is written into the five bits of the register 14 inverted. As a result of this, in the register 14 is recorded corrected, i.e. an error-free column, with which the next reproduced column is compared in the next cycle.

Thus, the controllable inverter block inverts the erroneous characters of the reproduced column in order to write to the register 14 the error-free value of this column.

After switching on the power supply of the device or after the synchronization of parallel playback, the process of correcting the inversion of the output signals of the buffer register 4 becomes false and this continues after the error-free reproduction of the columns

To automatically set up the measuring part of the device to its original, working state after turning on the power supply and after the reproducing clock pulses, a restoration circuit of the original state was intended.

The device is reset, i.e. It becomes ready to isolate errors after playing back at least two error-free columns. The first error-free column is entered by the fourth synchronization pulse of the previous clock cycle into register 1 In register 14; the same column is recorded as a distorted false action of block 13 of controlled inverters (for example, due to a fall of the table). The corresponding error signals are recorded in the memory register and are recorded by the error recording unit 8.

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The next, second error-free column is entered into the register F h th register 4, Block 12 adders produces the corresponding, i.e. with a shift by one bit, elementwise comparison of the value of the bits of the buffer register 4 with the information stored in the six bits of the register 15 and represented by the element 10 (modulo two). Since this column, which is in buffer register 4, and the previous column, stored in register 15, are unhygienic, a signal; errors on the outputs of the block 12 adders are missing. Accordingly, a signal is generated at the output of the element OR 11 and, therefore, at the first input of the element AND 16.

At the same time, the second synchronization pulse of this one also passes through AND 16 to the setup input of register 7 and zeroes it.

The fourth synchronization pulse of the same clock cycle into the register 14 is saved to: an error-free BTOPOPJ column from the buffer register 3 is written. The i i TOBO device detects errors.

In addition to organizing a test recording of a test signal in the form of a gsevd-random sequence both along and across the tape, the proposed device also has several advantages: it allows you to use not only a pseudo-watch sequence as a test signal, but also any other signal: Sequences of zeros (information signals at the inputs of the magnetic recording apparatus are absent) and ones, a dial-up fixed code. For the sake of this, it is enough to only modify the key elements 9 and 10. Thus, when using the code ... 1010 ..., two-input OR elements, respectively, connected to the outputs of registers 14 and 15, should be used as key elements 9 and 10.

In addition, the device allocates channels per channel at the outputs of register 7 and allows localizing the recording-reproduction channel with low reliability by turning off the bits of register 7 when executing it on D-triggers.

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Claims (1)

An apparatus for controlling a multichannel magnetic recording apparatus, comprising a master oscillator connected by an output to interconnected clock input of a magnetic recording apparatus and an input to a code generator connected by outputs through a magnetic recording apparatus to information inputs of a buffer register connected by a synchronizing input to interconnected the sync output of the magnetic recording apparatus and the input of the sync signal generator and the outputs to the first inputs modulo-two adders, connected by outputs to the inputs of the first register connected by a control input with a corresponding clock generator and outputs with inputs of the error recording block, the first and second key elements and the OR element, in order to reduce the error control by controlling the entire area of the magnetic carrier using a pseudo-random control signal, a second modulo-two block, a controllable inverter block, are entered into it, the second and third registers and the AND element connected by the first input through the OR element 128 to the outputs of the second block of adders modulo two, the second input to the corresponding output of the sync signal generator and the output to the set input of the first register connected by the outputs to the first inputs of the controllable inverter unit connected to the inputs of the second register and the second inputs to the connected outputs of the buffer register and the first inputs of the second block of adders modulo two, connected by the second inputs to the outputs from the first to the last but one digit of the third register connected syn the raining input to the synchronized input of the second register and the corresponding output of the clock generator and the outputs of the last and next to last bits to the inputs of the second key element connected by the output to the additional second input of the second block of modulators two, and the second register connected to the outputs from first to the last but one bit to the second inputs of the first block of adders / modulo two and outputs of the last and second to last bits to the inputs of the first key element connected to the output with an additional second input of the first block of modulo two adders. about Q / Q . L. -L i spike L Q aum / „.JB. Fi.g.2