JPS6215946B2 - - Google Patents

Description

DETAILED _DESCRIPTION OF THE INVENTION As shown in FIG. is encoded and the code signal is extended in the longitudinal direction of the tape, that is, the audio track T
Recording is performed on an auxiliary track _TQ parallel to _A and control track _TC . In addition,
The figure shows a case where one track _TV is formed for each field of the video signal.

A specific example is the SMPTE code.

As shown in Figure 2, one frame is 80
Therefore, the bit frequency is 2.4KHz.Of these 80 bits, 32 bits are used as a time code, 32 bits are used as free bits for the user, and 16 bits are used as a sync word. A 32-bit time code consists of a frame code, a second code, a minute code, and an hour code, each of which indicates the hour, minute, second, and number of the frame. divided into two,
Four user bits are inserted between each bit. The 16-bit sync word is used when the tape is running in the forward direction and therefore this SMPTE code signal is read in the direction shown by arrow F, but when the tape is running in the reverse direction and therefore this SMPTE code signal is read out in the direction shown by arrow F.
The state is such that it is possible to identify whether the SMPTE code signal is to be read out in the direction indicated by arrow R, and the code signal can be read out without error when traveling in any direction.

Note that this code signal is a so-called biphasic signal in which information of "1" and "0" is expressed by a difference in inverted phase as shown in the figure.

In this way, recording a signal indicating the absolute address of each frame of the video signal on the track _TQ extending in the longitudinal direction of the tape becomes convenient when editing the tape.

However, in the case of slow or still motion playback, the tape speed is slow or the tape stops, so this track T
There is an inconvenience that the code signal recorded in _Q cannot be read out.

The present invention makes it possible to reliably read a code signal indicating an absolute address even in slow motion or still motion playback, and to improve the efficiency of editing.

In the present invention, as shown with diagonal lines in FIG. 3, a code signal S _C indicating the absolute address of the track TV of the video signal is recorded in the track _{TV of} the video signal.

In this case, as shown in the figure, this code signal S
_C is inserted and recorded in both the odd and even fields of each frame. Furthermore, when reading out the code signal _SC , the present invention inserts check codes with predetermined contents into the code signal _SC at predetermined bit intervals,
It is possible to prevent incorrect reading due to fluctuations in the time axis of the code signal due to jitter, skew, etc., or due to slow motion or still motion playback, and to detect code errors. This is how it was done.

As an example, as shown as the shaded area in FIGS. 4A and 4B, a burst signal in any predetermined horizontal period excluding the vertical synchronizing pulse period T _VP and the equalization pulse period T _EP within the vertical blanking period may be used. It is inserted into the video section after S _B , and the same code signal is repeatedly inserted into each of three consecutive horizontal sections.

This code signal has a bit frequency _b that is, for example, a color subcarrier frequency _c (approximately
3.58MHz), for example, 1/2. If the horizontal frequency is _h and the vertical frequency is _v , then there is the relationship _c = 455/2 _h = 455 x 525/4 _v ...(1), so when _b = 1/2 _c ...(2) is _b = 455/4 _h ...(3). The arrangement of code signals in this example is shown in FIG. 4C. The code signal is the track _TV of the video signal.
Therefore, unlike the SMPTE code signal in Figure 2, there is no need to place a sync word at the beginning.First, a 2-bit sync bit shown as the shaded area in Figure 4C is placed, and after this sync bit, 4 bits are recorded. A frame code (the first frame number) follows, followed by 4 user bits. Thereafter, the time code (second code, minute code, hour code of 4 bits each) and user bits are arranged in series in the same arrangement as the SMPTE code in Figure 2, and sync bits are inserted at 10-bit cycles starting from the first sync bit. The total number of bits of these sync bits, time code, and user bits is 82 bits, and an error detection code for the information code, such as an 8-bit CRC code (cyclic redundancy check code), is added afterwards. The CRC code is encoded so that the information code is divided by a predetermined code to obtain a remainder. During decoding, this information code and the remainder (CRC code) are divided by the same predetermined code as during encoding, and the result is , if the code is divisible such that the remainder is zero, it is detected that there is no error, and if there is some remainder, it is detected that an error has occurred.This is a code that can detect burst errors.

FIG. 5A is an example of a code signal indicating an address to which the present invention is applied. A code is inserted from the leading edge of the horizontal synchronizing signal P _H at T _s (for example, 10.616 μs), and a 90-bit code is inserted. The horizontal synchronizing signal P H is inserted over a period of 50.286 μs, and the horizontal synchronizing signal P _H comes after a further period of 2.65 μs. Also, the drop frame bit is 1 in FIG. 5A. NTSC
In this method, 1 field is (1/59.94 second), so if you want to match the absolute time with the address specification, 1 field is (1/59.94 second).
It is necessary to skip only two frames every minute and not skip the next two frames every 9 minutes and 59 seconds. In order to match address designation and absolute time in this way, this bit is set to 1 to perform frame control. Similarly to the case of FIG. 2, the code signal in FIG. 5A indicates 23:59:59 seconds 29 frames.

In Fig. 5A, "1" and "0" are represented by different levels. For example, "0" is the pedestal level, and "1" is the 50IRE level.
units or higher level,
So-called NRZ modulation is performed. Here
NRZ modulation refers to a signal form in which "1" is a high level and "0" is a low level "0".

The SMPTE code signal recorded in the longitudinal direction of the tape uses the biphase modulation method as described above, and the signal itself contains a clock component, but in this case, the highest frequency of the signal and the bit frequency are equal. Become. However, in the code signal of this example, there are 80
In order to insert more information than bits, the bit frequency must be very high, so NRZ modulation is used, which allows the highest frequency to be 1/2 of the bit frequency.

Furthermore, for these reasons, a so-called self-clocking modulation method in which the signal itself has a bit clock component is not used, so sync bits, which will be explained in detail later, are inserted at predetermined bit intervals to periodically correct the timing. . 6th
The figure shows an example of a circuit for forming a code indicating the above-mentioned absolute address and inserting it into a video signal for recording.

In FIG. 6, 1 is a terminal to which a video signal to be recorded is supplied, and this video signal is supplied to a clamp circuit 2.
supplied to 3 is a synchronization separation circuit that separates a synchronization signal from a video signal, and 4 is a clamp pulse generation circuit that forms a clamp pulse from the synchronization signal. The video signal passed through the clamp circuit 2 is supplied to a synthesis circuit 6 via a vertical blanking period shaping circuit 5, and is also supplied to a synchronization separation circuit 7. A frame pulse separation circuit 8 to which the output of the synchronization separation circuit 7 is supplied separates a frame pulse, and this frame pulse is supplied to a time counter 9. On the other hand, the output of the synchronous separation circuit 7 is supplied to a monostable multivibrator (hereinafter referred to as monomulti) 10, so that the equalization pulse is removed, and a signal with a horizontal frequency _h is generated from the monomultivibrator 10. The signal is supplied to a phase comparator 11. The phase comparator 11, variable frequency oscillator 12, and timing clock generation circuit 13 are PLL.
A timing clock generation circuit 13 is formed by forming a circuit.
from Fig. 5 B to K along with the signal of frequency _h .
Clock pulses _P1 to _P10 shown in are generated, a signal with a frequency of _h is supplied to the phase comparator 11, and the comparison output is given to the variable frequency oscillator 12 as a control signal, synchronized with the horizontal synchronizing signal in the video signal. Clock pulses P ₁ to P ₁₀ are formed. This clock pulse P ₁ has a frequency of carrier color frequency _c ,
Clock pulse P ₂ is of 1/2 _c , and one period of clock pulse P ₂ is equal to one bit of the code signal of FIG. 5A. Furthermore, clock pulse P ₃ is of 1/4 _c . The timing clock generating circuit 13 is constructed so that the clock pulses _P4 to _P6 are formed from the clock pulse _P3 by a decimal counter, and the clock pulses _P7 to _P10 are formed by a hexadecimal counter.

The clock pulse from the timing clock generation circuit 13 and the output of the time counter 9 are applied to the time code encoder 14 to form time codes (frame code, second code, minute code, and hour code), which are sent to the synthesis circuit 15. Supplied. At the same time, a sync bit is generated from a clock pulse from a timing clock generator 13 in a sync bit generator 16, a user bit is generated in a user bit encoder 17, and these sync bits and user bits are supplied to a synthesizing circuit 15. Therefore, the synthesis circuit 1
At the output of 5, a code signal in which the time code, user bits and sync bits are arranged as shown in FIG. is added in the synthesis circuit 19
A code signal as shown in FIG. 4C is generated at the output. This code signal is supplied to the gate circuit 20. The gate circuit 20 generates gate pulses corresponding to three consecutive water intervals within the vertical blanking period based on the vertical synchronization pulse separated by the vertical synchronization separation circuit 21 from the output of the synchronization separation circuit 7. formed and supplied by the circuit 22;
The code signal is gated by this gate pulse and supplied to the synthesis circuit 6. The combining circuit 6 is supplied with a video signal from which codes that may have already been inserted in the vertical blanking period have been removed by the vertical blanking period shaping circuit 5 using the gate pulse from the gate pulse generating circuit 22. . Therefore, at the output terminal 23 of the synthesis circuit 6, a video signal in which a code signal is inserted into each of the three consecutive horizontal sections within the vertical blanking period appears, and this video signal is input to the VTR including the FM modulator, etc. It is recorded on magnetic tape via a signal recording system.

Note that, for example, an SMPTE code is supplied from the outside to the terminal 24, and this is preset to the time counter 9 via the decoder 25 and the preset switch 26 when the preset switch 26 is turned on. The time codes inserted into the signal may have a synchronous relationship.

FIG. 7 is a block diagram showing an example of a circuit for reproducing a video signal including a code signal indicating the absolute address recorded in this manner and extracting the code from the reproduced video signal.

In FIG. 7, reference numeral 31 denotes a terminal to which a reproduced video signal is supplied. A code signal is extracted from this video signal in the following manner, and this code signal is obtained at an output terminal 32. First, the video signal is supplied to the code separation circuit 33, and the code signal is separated from the video signal by the synchronization signal separated by the synchronization separation circuit 34. Also, N of bit frequency _b
An oscillator 35 that oscillates at a frequency twice as high (N is a positive integer, for example, 16 times) is provided, and the output of the oscillator 35 is
is supplied to a hexadecimal counter 36, and this counter 3
The output of 1/ _2c of 6 is supplied to a decimal counter 37, the output of this counter 37 is supplied to a hexadecimal counter 38, and the clock pulses _P1 and _P2 at the time of recording mentioned above appear from the counter 36. The aforementioned clock pulses P ₃ to _{P 6} appear from the counter 37, and the clock pulses P 3 to P 6 appear from the counter 37.
The aforementioned clock pulses P ₇ to P ₁₀ appear from there. However, these clock pulses _P1 to _P10 are arranged to have a synchronized relationship with a code signal separated from the reproduced video signal. For this reason, from the separated code signal shown in Figure 8A, the monomulti 39 outputs a signal that is slightly shorter than one horizontal interval as shown in Figure 8C.
A pulse _P11 is formed for a period longer than that of the 90-bit code signal, and the code signal is also supplied to the edge pulse generation circuit 40 to form an edge pulse at the falling edge of the code signal. Furthermore, the output of the counter 37 is supplied to the sync bit gate pulse generation circuit 41, which forms the sync bit gate pulse _P12 shown in FIG. 8B, which becomes " ₁ " at the phase corresponding to the sync bit, similar to the clock pulse P6. be done.

Now, suppose that a code signal including 10 sync bits is separated from a video signal as shown in FIG. occurs, and this edge pulse and C
The sync bit gate pulse P ₁₂ shown in FIG. Supplied. Therefore, the output pulse of 1/2 _c of the counter 36 is synchronized with the code signal by correcting the phase difference τ with respect to the timing of the code signal, as shown in FIG. 9D. This allows the timing of the clock pulse to be synchronized with the reproduced code even if the time axis of the reproduced video signal varies from the normal one due to jitter or slow motion reproduction. However, since the sync bit is inserted every 10 bits, it is possible to achieve highly accurate synchronization. Further, in this example, the oscillator 35 is a fixed oscillator, but if it is configured to be phase-locked to, for example, a horizontal synchronization signal in the reproduced video signal, the range in which timing can be synchronized can be further expanded.
It is possible to read the code signal from still playback when the magnetic tape is stopped to when the magnetic tape is played back at several times the normal speed. Note that the counters 37 and 38 are reset at the rise of the output pulse _P11 of the monomulti 39 via the AND gate 45.

Output pulses from these counters 36, 37, and 38 are supplied to a timing pulse generation circuit 46 to generate necessary timing pulses.
Further, the code signal separated by the output pulse from the counter 36 is supplied to a serial/parallel conversion circuit 47 consisting of a shift register, and the time code and user bits (64 bits in total) excluding the sync bit and CRC code from the code signal are Bit by bit is converted into parallel code. This parallel code is for example
The data are sequentially written into a buffer memory 48 consisting of a RAM, and are also supplied to a code check circuit 49.

As shown in FIG. 8E, the code check circuit 49 receives a timing pulse P 14 from the serial/parallel conversion circuit 47 by being supplied with a timing pulse P ₁₄ from the timing pulse generation circuit 46 corresponding to the position of the time code.
It decodes the bit time code and checks whether the result is an impossible number in each digit. For example, due to a dropout, the hour code of the time code becomes 27 o'clock, or the second code becomes 81.
This is to check that the time is within seconds. As a result of this check, a determination output is generated from the code check circuit 49 which is "1" if it is correct and "0" if it is incorrect.

Also, the code signal from the code separation circuit 33
The signal is supplied to the CRC code check circuit 50.
The CRC code check circuit 50 includes a timing pulse generator circuit 46 as shown in FIG. 8D.
A pulse _P13 having a phase matching the position of the CRC code is generated, the code signal including the CRC code is divided by a predetermined code signal, and it is calculated whether or not the remainder becomes zero. If the remainder is zero, it is determined to be correct.
If the determination output of the CRC code check circuit 50 becomes "1" and the remainder does not become zero, it is determined that there is an error and the determination output becomes "0".

Furthermore, the aforementioned sync bit gate pulse _P12 (FIG. 8B) is supplied to the gate circuit 51, and the sync bit extracted from the code signal is supplied to the sync bit check circuit 52, which generates a timing pulse. By supplying a pseudo sync bit from circuit 46, it is checked whether the sync bit is correct. The determination output of the sync bit check circuit 52 is "1" when the sync bit is correct, and "0" when the sync bit is incorrect.

Discrimination outputs from this sync bit check circuit 52, the aforementioned code check circuit 49, and CRC code check circuit 50 are supplied to an AND gate 53. When the output of the AND gate 53 becomes "1", that is, when it is detected that there is no error in the code signal, the hold circuit 54 uses the timing pulse from the timing pulse generation circuit 46 to generate "1" as shown in FIG. A pulse P ₁₅ of 1” is generated. This hold circuit 54 is connected to the vertical sync separator circuit 55 connected to the sync separator circuit 34 as shown in FIG.
It is reset by the vertical synchronizing pulse _TVP shown in FIG. In this way, the output pulse _P15 of the hold circuit 54 is inverted and supplied to the AND gates 44, 45, and when the pulse _P15 becomes "1", resetting of the counters 36, 37, 38 is prohibited, and the pulse _P15 is The signal is inverted and supplied to the AND gate 56 and also to the memory pulse generation circuit 57. AND gate 56 is buffer memory 4
8, and while the pulse _P15 is “0”, the serial/parallel converter circuit 47
The 4-bit code from
When the pulse _P15 becomes "1", this writing is prohibited. Then, the memory pulse generation circuit 57 generates a memory pulse P ₁₆ synchronized with the rising edge of the pulse P ₁₅ as shown in FIG. A write clock pulse is provided to buffer memory 59 and the contents of buffer memory 48 are transferred to buffer memory 59. Then, a read address signal is supplied from the terminal 60, and a total of 64 bits of data consisting of a time code and user bits is outputted to the output terminal 32. This data is supplied to a display device, an editing device, etc.

As mentioned above, the code signal is inserted into three consecutive horizontal sections within the vertical blanking period, but if the code signal in the first horizontal section is mistakenly inserted, the pulse _P15 from the hold circuit 54 Does not start up, buffer memory 48 to buffer memory 5
No data is transferred to 9, and similar error detection is performed on the code signal of the next horizontal section.
Then, only error-free code signals are stored in the buffer memory 59. Therefore, the position at which the code signal is inserted within the vertical blanking period does not need to be inserted into consecutive horizontal periods, and if any position within the vertical blanking period is correctly read, it will be held.

In the above embodiment, a code signal indicating the absolute address of the track is recorded in the track _TV , but it is also recorded in the track _TQ extending in the longitudinal direction of the tape in FIG. 2 or 3. The same code signal as that recorded in the track _TV or an SMPTE code signal may be recorded using the biphase method.

According to the above-described magnetic recording and reproducing apparatus according to the present invention, a code signal indicating the absolute address of this track is recorded not on a track extending in the longitudinal direction of the tape but on a track of a video signal. Even in the case of still motion reproduction, the code signal indicating this absolute address can be reliably read, making editing more efficient.

Moreover, in the present invention, a signal indicating an absolute address is inserted into the horizontal video section between horizontal synchronizing pulses, rather than by modifying synchronizing pulses, so it is not necessary to clamp the video signal or change the synchronizing signal during playback. There is no adverse effect on signal processing such as separation.

Furthermore, since the present invention inserts a check code with predetermined bit content at predetermined bit intervals into a code signal indicating an absolute address, it is possible to detect errors using this check code, and also to detect pulses synchronized with the check code. By forming this, the reproduced code signal can be reliably read.

Furthermore, the present invention modulates the code signal using NRZ modulation, and the highest frequency can be set to 1/2 of the bit frequency. Therefore, a signal of 80 bits or more can be inserted within a predetermined horizontal section of the vertical blanking period. Even if the signal component is too high, it will not penetrate into the color subcarrier band. Also, in the case of NRZ modulation,
Although it does not have a bit clock component, according to the present invention, sync bits are inserted at predetermined bit intervals and the timing of the read clock pulse is periodically corrected thereby. Even if the code varies from the normal value, the code signal can be reliably read.

[Brief explanation of the drawing]

Figure 1 shows an example of the recording pattern of a tape on which SMPTE code signals are recorded, and Figure 2 shows
FIG. 3 is a diagram showing an arrangement of SMPTE code signals, FIG.
Figure 6 is a diagram used to explain the video signal and code signal recorded by the magnetic recording and reproducing apparatus according to the present invention.
The figure is a system diagram of an example of a circuit for forming and inserting a code signal indicating an absolute address, FIG. 7 is a system diagram of an example of a circuit for reading this code signal, and FIGS. It is a waveform diagram used for explanation. T _Q is a track extending in the longitudinal direction of the tape,
_TV is the recording track of the video signal, and S _C is the recording part of the code signal indicating its absolute address.

Claims (1)

[Scope of Claims] 1. In a magnetic recording and reproducing device for recording and reproducing a video signal forming one diagonal track for each field or frame on a magnetic tape, the absolute address of the video signal is indicated at a predetermined bit interval. An address code signal which is NRZ modulated and has a sync bit code consisting of at least 2 bits including a bit pattern of (“1”, “0”) or (“0”, “1”) for each video signal is an oscillator that generates a clock that is inserted into a predetermined horizontal section of the vertical blanking period for recording and that has an oscillation frequency that is N times the bit frequency of the address code signal (N is a positive integer) during reproduction; The address code signal reproduction output is read by a read clock generated by a read clock generation circuit consisting of an N-ary counter that divides the frequency by N. ) or (“0”, “1”) bit pattern to synchronize the read clock and the address code signal by resetting the N-ary counter at the falling or rising timing of the level generated by the bit pattern. A magnetic recording and reproducing device.