SE419278B - SET UP AND DEVICE FOR INFOING AN ADDRESS SIGNAL IN A VIDEO SIGNAL - Google Patents

Description

_ '?? 12 "Û96 ° 2 for a selected image can not be easily produced with the systems according to the prior art. In the Time Code signals, each television picture identifies, but the identification of the smooth or odd sub-picture of the picture as well as the identification of the phase of the color sync signal in each TV sub-picture are impossible.

Exact editing can therefore not be achieved with the prior art systems.

In order to obtain an address signal in a video recorder with the possibility of still picture reproduction during such still picture reproduction, it has been proposed that the synchronizing signal in a picture blanking period of a television signal be converted into a signal corresponding to an address.

Japanese Patent Specification 42/4540, filed by Nippon Hoso Kyokai and published February 24, 1967, discloses, for example, this procedure. This Japanese patent specification describes an address signal which includes image identification, which can be reproduced even in still image reproduction, but since there is no normal synchronization pulse in the image blanking period, a special processing is necessary for feeding the reproduced address signal to other video recorders and a time base correction device.

Since in these prior art devices an address signal is recorded for each image, read errors, caused by omissions or bandwidth noise during playback, cannot be prevented. now; object of the present invention is to provide a method of inserting an address signal into a vertical range of a video signal. Another object of the invention is to provide a method of registering an address signal which prevents read errors.

A further object of the invention is to provide a method of inputting an address signal which includes an error checking code.

Yet another object of the invention is to provide a method of recording an address signal which is suitable for a spiral scan VCR. Yet another object of the invention is to provide a method of inputting an address signal, which method overcomes the time base error.

Yet another object of the invention is to provide a circuit which can read an address signal without error. Yet another object of the invention is to provide a circuit which produces an address signal from a VCR independent of the tape speed. The invention will be described in more detail in the following with reference to the accompanying drawings. Fig. 1 is a plan view of a part of a magnetic tape, on which a video signal is recorded as slanted tracks and an address signal is also recorded by a method according to the prior art. Fig. 2 is a schematic diagram generating a time code signal SMPTE recorded on the tape.

Fig. 3 is a plan view of a part of a magnetic tape, on which a video signal and address signals are registered by the method according to the invention. Figs. 4A and 4B are diagrams illustrating a pattern of signals recorded on a tape according to the invention. Fig. 4C is a schematic diagram illustrating a time code signal according to the present invention, which signal is recorded on the tape.

Fig. 5A is a diagram illustrating a pattern of signals recorded on the tape according to the invention. Figs. SB-5K, 8 and 9 illustrate waveforms used to explain the operation of the circuit of the present invention. Fig. 6 is a block diagram illustrating a circuit according to the invention for generating the time code signals and recording them on a magnetic tape. Fig. 7 is a block diagram illustrating a circuit according to the invention for reading the time code signals from a magnetic tape and decoding the address.

Fig. 1 illustrates a prior art method for recording an address signal on a magnetic tape T, in which in addition to a video signal the address signal is recorded.

In Fig. 1, the TV represents a number of video tracks, which are formed on the magnetic tape T and each of which contains a video signal for a sub-picture. Of course, the video signal for an image can be recorded on a video track. TA indicates a track on the band T, in which track the audio signal is registered. In a track TQ the queue signals are registered and in a track TC the control signals are registered. An address signal is registered in the queue track TQ. In this case, a time code signal SMPTE is used as the address signal and two video tracks Tv, which form an image, are identified by a time code signal SMPTE.

The time code SMPTE is approved as a time and control code according to the American National Standard for video and audio tapes for television systems with 525 lines and 60 frames from April 2, 1975 and is published in the journal for SMPTE, volume 84, July 9, 1975.

As shown in Fig. 2, which schematically illustrates the code signal SMPTE, each address corresponds to an image and contains 80 bits, numbered 0-79, and the bit frequency is selected as 2.4 kHz. As illustrated in Fig. 2, the time address bits consist of 26 bits which indicate image 29, second 59, minute 59 and hour 23. Bit number l0 is the image exclusion ~ "fiï fi ifšß fl âé-Z ~ 4 flag, bits nos. L1, 27, 43, S8 and S9 are unassigned address bits and bits Nos. 4-7, 12-15, 20-23, 28-31, 36-39, 44-47, 52-55 and 60-63 are user bits. The synchronization word of 16 bits is arranged so that it can be determined whether the band is transported in the forward direction and thus the time code signal SMPTE is read in the direction indicated by an arrow F or the band is transported in the reverse direction and thus the time code signal SMPTE is read in the direction indicated by an arrow R. the direction. The time code signal can thus be read correctly regardless of whether the tape is transported in one or the other direction. In this case, the code signal is recorded so that its information "1" and "0" is recorded as a two-phase mark, as illustrated in Fig. 2.

If the address signal for each image of the video signal is recorded in the manner described above in the track TQ, which extends in the longitudinal direction of the tape T, editing of the tape can be performed very quickly and accurately; However, in the case of slow motion reproduction or still image reproduction, the speed of the tape becomes very low or the tape is stopped, so that the code signal registered in the track TQ cannot be read.

Figs. 3-9 illustrate an example of the invention which provides an address signal which can be locked even in slow reproduction or in still image reproduction, whereby the tape can be effectively edited. The video signal in the NTSC system was used as an example.

Fig. 3 is a plan view of a magnetic tape T, on which the video signal and the address signals are recorded by the method and the device according to the invention.

According to the invention, an address signal SA, which identifies a video signal corresponding to each track TV, is input to the video signal as a digital signal, and the video signals are recorded on the tape as slanted tracks TV. The address signals SA recorded in the video tracks TV are indicated as slanted areas in Fig. 3. The address signals SA are inserted in the video signals for odd and even fields in an image and are then recorded, as shown in Fig. 3.

According to the present invention, the time code signal comprises synchronization bits which are inserted in the time code signal at predetermined intervals and then recorded in the video track TV, so that by correcting the phase of the clock with the predetermined intervals by using the synchronization signal in its reading, the address signal can be read and read. , even if the bit rate of the code signal varies by flutter, skew and other interference factors or by the variation in the line frequency during low speed reproduction and still image reproduction.

Furthermore, in order to avoid errors in reading, according to the present invention, an error control code is arranged in the code signal.

As shown in italics in Figs. 4A and 4B, which include a recorded pattern of signals on the band not shown in accordance with the invention, an address signal is entered in a line period of the suppressed line period within the image blanking period or the vertical interval of except for the part that includes an image synchronization pulse period TVP and the smoothing pulse period TEP. The address signal is entered in the period after color sync signals SB and it is desirable that the same address signals be entered repeatedly in three consecutive line periods. In the following, the address signal will simply be referred to as the "VITC Uvertical interval time code" signal. The above suppressed periods correspond to the line periods l0-21 in the NTSC system.

The VITC bit frequency fB of the signal is selected as the color carrier frequency fsc, which is equal to 3.58 MHz, divided by an integer, for example half the frequency fsc. If the line frequency is called fH and the frame rate fv, the following relationship is established: = åf = 4ssxszsf (l) fsc 2 H 4 V If the following relationship is established: EB = NIF * fsc (2) the following equation 3 is obtained: fr: = i? fn (3) With reference to Fig. 4C, the arrangement of the code signal according to the invention will be explained. The code signal is recorded in the video track Tv, so it is not necessary to use the synchronization word at the top of the time code signal SMPTE, shown in Fig. 2. First, two synchronization bits are placed at the top of the code signal, as shown by a dashed portion in Fig. 4C. Synchronization bits, each comprising two bits, are placed at ten-bit intervals and are shown by dashed portions in Fig. 4C. Thus, bits Nos. 0, 1, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51, 60, 61, 70, 71, 80 and 81 are synchronization bits. The time address bits are arranged in a manner similar to the bits in the time code SMPTE. Bits no. 2-5 are picture- moms-z 6 number, 12-13 are kšiiatiøtai, 22-25 are secondary, 32434 ar second! tens, 42-45 is minute, 52-54 is minute, 62-65 is hourly and 72-73 is hourly. Bit no. 14 is the image exclusion flag, bit no. 15šh: one-part image mark, bit numbers 35, 55, 74 and 75 are unassigned address bits and bits no. 66-69 and 76-79 are user bits.

By making bit No. 15 equal to "0" for the first and third fields or "1" for the second and fourth fields, field identification can be achieved as to whether the field is even or odd. The total number of these information bits, synchronization bits, time code bits, user bits, etc. is 82 bits. After these bits of information, an error check code for the previous code is provided by, for example, a cyclic redundancy check code (hereinafter referred to as CRC code), which consists of eight bits.

Using the CRC code, the data presented is divided between bit 0 and bit 81 (a total of eighty-two bits) with a predetermined code or polynomial (constant, x8 + 1), and the remainder or remainder is encoded into the last eight bits. The last eight bits are then the CRC code. In decoding, all ninety bits, including the CRC code, are divided by the predetermined code, which is constant and can be expressed by x8 + 1. The predetermined code used in the decoding method is the same predetermined code used in the encoding process. The remainder or residue acts as an error indicator. If there is a residue or residue, the information is incorrect, otherwise the information is correct.

Fig. 5A illustrates an example of the time code signal representing an address according to the present invention. The code signal, which consists of ninety bits, is inserted in the period of 50.286 μs and is inserted from the time Ts (for example 10.616 μs) after the leading edge of the line synchronizing signal until the time 2.65 μs before the leading edge of the following line synchronizing signal. The code signal illustrated in Fig. 5A indicates the address of Fig. 29, second 59, minute 59, hour 23, i.e. the same address as that shown in Fig. 2.

In this case, it is sufficient that the information "1" and "0" in the signal VITC are expressed as NRZ signals of different levels, as shown in Fig. 5A. For example, the information "0" is selected as the socket level and the information "1" is selected as 50 IRE units or a signal higher than the level "0", and the signals are then registered with the opposite level to the line synchronizing pulse, seen from the socket level. Fig. 6 illustrates a circuit for generating the signal VITC and for recording it on a magnetic tape.

In Fig. 6, an input terminal 1 receives a video signal to be recorded. The video signal is supplied to a latch 2 and to a sync signal separator 3, which separates a synchronizing signal from the video signal. A locking pulse generator 4 generates a locking pulse from the synchronizing signal. Via the latch 2 the video signal is fed to an addition circuit 6 via an image blanking period shaping circuit 5 and also fed to a sync signal separator 7. Image pulses are separated by an image pulse separator 8 which receives the output signal from the sync signal separator 7. The image pulses are fed to a timer 7. to a monostable multivibrator 10. The monostable multivibrator 10 removes an equalization pulse from the signal and generates a signal with a line frequency f fl, which is applied to a phase comparator 11. The phase comparator 11, a variable frequency (VFO) oscillator 12 and a clock generator 13 form a phase locked loop. The clock generator 13 generates a signal with a frequency fH and clock pulses P1-P10, shown in Figs. 5B-SK.

The signal generated by the generator 13 with the frequency fH is applied to the phase comparator 11 for comparison with the input signal from the monostable multivibrator 10. The resulting output signal from the phase comparator 11 is applied to the oscillator 12 as a control signal. The clock pulses P1-P10 are thus generated synchronized with the line synchronizing signal of the video signal. 7 The clock pulse P1 has the same frequency as the color carrier frequency fsc. The clock pulse P2 has a frequency of 1/2 fsc and a period of the clock pulse P2 is equal to a bit cell in the code signal shown in Fig. SA. The clock pulse P3 also has a frequency of 1/4 fsc. The clock generator 13 is designed to generate the clock pulses P4-P6 by means of a decimal counter from the clock pulse P3 and the clock pulses P7 ~ P10 by means of a hexadecimal counter. The clock pulses from the clock generator 13 and an output signal from the timer 9 are applied to a time encoder 14 to form a time code (image code, second code, minute code and hour code), which is applied to an adder circuit 15. At the same time, synchronization bits are formed by a synchronization bit generator 16. from the clock generator 13 and user bits are formed in a user bit encoder 17. These synchronization bits and user bits are supplied to the adder circuit 15. The output signal from the adder circuit 15 is consequently the code signal, which consists of the time code, the user bits and the synchronization bits arranged in Figs. the way. The output signal from the adder circuit 15 is then applied to a CRC encoder 18. The code signal shown in Fig. 4C is then obtained from an adder circuit 19, added to the CRC code from the CRC encoder 18. The code signal is applied to a gate circuit 20.

At the same time, gate pulses corresponding to three consecutive line periods in the image blanking period are generated at the gate pulse generator 22 on the basis of an image synchronization pulse which is separated by an image sync signal separator 21 from the output of the sync signal separator 7. The gate pulses are then fed to the gate circuit 20. the gate signal The gate controlled code signal is thus fed to the adder circuit 6. A code signal, which may have been introduced during the image blanking period, is removed in the image blanking period shaping circuit 5 from the video signal by the gate pulse control from the gate pulse generator 22. The output signal from the circuit 5 is then fed to the circuit 5. The video signal, in which the code signals are input for three consecutive line periods within the image blanking period, is thus obtained from an output terminal 23. The output video signal is recorded on a magnetic tape via a signal recording system in the video recorder, which includes a frequency modulator and so on.

It is further possible to output the SMPTE time code from a terminal 24 and synchronize that code with the time code to be inserted into the video signal. The synchronization can be achieved by presetting the timer 9, when a presetting switch 26 is turned on.

The SMPTE timing code is supplied via a decoder 25 and the preset switch 26. In the block diagram of Fig. 7, a circuit according to the invention for displaying the video signal is illustrated, which is recorded on the tape in the manner explained above, the code signal being read from the video signal and the address is decoded. In Fig. 7, an input terminal 31 receives a video signal reproduced from the video signal recorded in the track TV.

The code signal is generated on an output terminal 32 in the following manner.

First, the video signal is fed to a code separator 33. The code signal is separated from the video signal by a synchronizing signal which is separated from the video signal in a sync signal separator 34. An oscillator 35 is provided which oscillates at a frequency n times the color carrier frequency fsc (where n is integers, for example 8).

An output signal from the oscillator 35 is fed to a hexadecimal counter, 1v12oss-2 36. An output signal from the hexadecimal counter 36 with a frequency of 1/2 fsc is fed to a decimal counter 37. An output signal from the decimal counter 37 is fed to a hexadecimal counter 38. The clock pulses P1 and P2, which are the same as the registration pulses, are thus obtained from the counter 36, the clock pulses P3-P6 are obtained from the counter 37 and the clock pulses P7-P10 from the counter 38. These pulses are synchronized with the code signal which is separated from the reproduced the video signal.

A monostable multivibrator 39 produces a pulse P11 which is narrower than a line period but wider than the period where the ninety bit code signal is present, as shown in Fig. 8C, while an edge pulse generator 40 produces an edge pulse corresponding to a trailing edge of the code signal. - len.

The output signal from the counter 37 is applied to a sync bit gate pulse generator 41 for generating a sync bit gate pulse P12, shown in Fig. 88, which pulse is similar to the clock pulse P6, which has a value "1" at the phase corresponding to synchronization bits.

It is now assumed that the code signal, including synchronization bits "(10)", as shown in Fig. 9A, is separated from the video signal.

The edge pulse generator 40 then generates an edge pulse which corresponds to (is synchronized with) the trailing edge of the code signal, as shown in Fig. 9B.

This edge pulse and the sync bit gate pulse P12, shown in Fig. 9C, are applied to an AND gate 42 for producing only one edge pulse which is synchronized with the trailing edge of the sync bit.

This edge pulse is applied to the counter 36 as a reset pulse via an OR gate 43 and an AND gate 44. As shown in Fig. 9D, the phase difference 1 between the output of the counter 36 is corrected with the frequency 1/2 fsc and the time position of the code signal and the output of the counter 36 is synchronized with the code signal. Even when the time base varies from the normal time base by fluttering or reproduction at low speed, by the above-described construction the time state of the clock pulse is synchronized with the reproduced code. The synchronization bits are further entered for every tenth bit, so it is possible to achieve a very accurate synchronization.

In the above example, the oscillator 35 is a fixed oscillator.

However, such an oscillator which is phase locked to, for example, the line synchronizing signal of the reproduced video signal can further expand the scope of the time mode which can be synchronized. It is then possible to read the code signal even in still image reproduction, whereby the magnetic tape is stopped, as in reproduction at high speed, the tape being driven at a speed which is several times higher than the normal speed. the playback speed. The counters 37 and 38 are reset by the leading edge hose pulse P11, which is an output signal from the monostable multivibrator 39, via an AND gate 45.

The outputs from the counters 36, 37 and 38 are fed to a beat pulse generator 46 to generate the required beat pulses.

The code signal separated from the code separator 33 and the output pulse of the counter 36 are fed to a series-parallel conversion circuit 47, which includes a shift register for reordering the code signal except for synchronization bits and the CRC code, i.e. time codes and user bits (in all sixty-four bits). to parallel codes, where each code consists of four bits.

These parallel codes are written into a buffer memory 48 in a direct access memory and are also fed to a code control circuit 49.

The code control circuit 49 decodes the time code, which consists of four bits and is supplied from the circuit 47 by the clock pulse P14, corresponding to the time state of the time code signal, shown in Fig. 8E, generated by the clock pulse generator 46, and checks the decoded numbers to determine if these are possible numbers or not. There are some possibilities that, for example, the hour code indicates hour 27 or that the second code shows second 81, which codes are obviously incorrect, caused by omission.

The code check circuit 49 generates a signal "1" when the code is correct, and a signal "0" when the code is incorrect.The code signal from the code signal separator 33 is supplied to a CRC code check circuit 50.

The pulse P13 shown in Fig. 8D, which coincides with the phase of the CRC code generated by the clock pulse generator 46, is fed to the CRC code control circuit 50. In the CRC code control circuit 50, the code signal, which includes the information code and the CRC code ( a total of ninety bits) with the predetermined code or the predetermined polynomial (constant) and the rest is checked. If there is no residue, the code is correct, with circuit 50 generating a signal "1". When there is a residue, the code is incorrect and the circuit generates a "0" signal.

Furthermore, the synchronization bits are separated from the code signal by gate control at a gate circuit S1 by means of the sync bit gate pulse P12, shown in Fig. 8B. The separated synchronization bits are applied to a sync bit control circuit 52. Whether or not the synchronization bits are correct is controlled by the expected synchronization bits from the clock pulse generator 46. If they are correct, the circuit 52 generates a signal "1", and if not, a signal "0" is generated. The outputs of the sync bit control circuit 52, the code control circuit 49 and the CRC code control circuit 50 are supplied to an AND gate 53. When the output of the AND gate 53 is "1", which means that the code signal is correct, a holding circuit 54 generates a pulse P15, which is "1", shown in Fig. 8G, by means of the beat pulse from the beat pulse generator 46. The holding circuit 54 is reset by an image sync pulse T VP 8F) from the image sync separator 55, which is connected to a sync separator (shown in Fig. 34). P15 from the holding circuit 54 is fed to the AND gates 44, 45. The proximity pulse P15 becomes "1", thus resetting of the counters 36, 37 and 38 is forbidden.The pulse P15 is fed to an AND gate 56 and a memory pulse generator 57. AND gate 56 outputs a write clock pulse to the buffer memory 48. During the period when the pulse P15 is "0", four bit codes from the series-parallel conversion circuit 47 are continuously written into the buffer memory 48, but when the pulse P becomes "1" it is forbidden. writing in memory.

The memory pulse generator 57 generates a memory pulse P16, which coincides with the leading edge of the pulse P 5, as shown in Fig. 8G. By feeding the memory pulse P16 to the AND gate 58, a write clock pulse is fed to a buffer memory 59 via the AND gate 58. The contents of the buffer memory 48 are thus transferred to the buffer memory 59. The output, which consists of the time code and the user bits (a total of sixty-four bits), is obtained. is held at the output terminal 32 by supplying a read address signal via a terminal 60. The read data is fed to a presentation and / or editing device.

As previously mentioned, the code signals are introduced in three consecutive line scan intervals during the image blanking period. If the code signal introduced in the first line period is incorrect, the pulse P15 from the holding circuit 54 does not rise, so data is not transmitted from the buffer memory 48 to the buffer memory 59. The next line period code signal is checked in the same way. Then only the correct code signal is stored in the buffer memory 59. It is then not necessary to enter the code signals in successive line intervals. The code signal can be entered in any of the intervals, if it is not the useful scan period. The number of repetitions of the code signal is furthermore not limited. Even if only one of the code signals is read correctly, the holding circuit 54 generates the pulse P15 and the system according to the invention works satisfactorily.

In the above example, the code signal, which represents an address, is registered in the track Tv. At the same time, the time code signal SMPTE, which viizass-2 12 represents the same address as recorded in the track Tv, can be recorded in the track TQ, which extends along the longitudinal direction of the magnetic tape. The time code signal SMPTE can be registered as a two-phase signal in the same way as the signal registered in the track TV.

Since an address signal indicating a video signal is registered as a digital signal in the track of the video signal, the digital signal corresponding to the address can be read directly even in slow motion or still image reproduction, and thus editing of the video tape can be performed very efficiently. the construction of the recording device according to the present invention.

In the invention, the synchronizing pulses and the other pulses are not processed but the address signal is introduced in the line period between the line synchronizing pulses within the image blanking period, so that no undesired effect is caused on such signal processing as locking of the video signal, separation of the synchronizing signal, etc. .

The bit rate fB of the input VITC signal is selected to be equal to the color carrier frequency fsc divided by an integer, so that if the video signal with the VITC signal is passed through the time base corrector, the reproduced video signal is written into the memory of the clock pulse, the frequency is higher than the color carrier an integer factor and the written signal is read from the memory to correct the time base. The clock references are thus the same in number at each bit cell in the address signal and the state of the address code is not affected by the time base correction.

According to the invention, further, synchronizing rivets are inserted at intervals of a predetermined number of bits in the code signal, so that reading errors can be checked with the synchronizing bits and by forming pulses synchronized with the synchronizing bits, reading of the code can be accurately achieved. noise factors or by varying the line frequency at slow motion or still image reproduction.

According to the invention, the error control code in the CRC code is added to the code signal, so that reading of the code signal can be achieved more accurately. The examples of the invention described above correspond to the cases where the video signal in the NTSC system is used, so that the bit rate of the VITC signal is selected as å fsc (where n is an integer). When video

Claims (8)

Signals in other systems, such as the PAL systems and other types, are used, it is necessary that the bit rate of the VITC signal be selected taking into account the predetermined relationship to the line frequency, so that all the bits in the signal VITC can be introduced in a line period, for example 455 / 4 fH line frequency). PATENT REQUIREMENTS A method of inserting an address signal into a video signal, characterized by the measures of providing the address signal with a plurality of time code bits, corresponding to the video signal recorded in a track and comprising synchronizing bits at intervals of a predetermined number bits, selecting at least one predetermined line period in each frame or picture of the video signal and inserting the address signal in the selected line. 2. A method according to claim 1, characterized in that the address signal is followed by an error check code signal. 3. A method according to claim 1, characterized in that the error control code is a cyclic, redundant control code. 4. A method according to claim 1, characterized in that the bit frequency of the address signal is selected as l / N of the color carrier frequency, where N is an integer greater than l. 5. A method according to claim 1, characterized in that the bit frequency is half the color carrier frequency. 6. A method according to claim 1, characterized in that the address signal comprises a field identification bit. 7. A method according to claim 1, characterized in that the selected, predetermined line period is within an image blanking period. Device for generating a video signal with an address signal, characterized by means for providing the address signal corresponding to a sub-picture or picture in the video signal, the address signal consisting of a plurality of time code bits, means for providing a cyclic redundancy check code signal for the address signal , means for selecting at least one predetermined line period within an image blanking period for each frame or image in the video signal and means for inputting the address signal in the selected line period. BEFORE PUBLICATIONS: