JPS601675A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To detect easily and assuredly an error due to the miserasion of the preceding data by performing the error detection based on the coincidence of index codes for each reproduced data block. CONSTITUTION:The same index code are stored every for blocks, for example, to registers 4 and 5 which are controlled by a synchronizing circuit 10 to a series of continuous data blocks given from a cyclic redundancy check (CRC) detecting circuit 2 for each reproduced data block. When the coincidence is obtained between contents of registers 4 and 5 with no attachment of dust, etc., a detection signal register 7 is renewed by the contents of the reister 5, etc. via a comparator 6. When the coincidence is obtained between contents of registers 7 and 5, an AND gate 9 is opened via a comparator 8. Then a decoder 3 is controlled by a signal showing no existence of error based on the result of a CRC check carried out by the circuit 2, and the reproduced data containing a parity check signal given from the circuit 2 is written to the decoder 3. In such a constitution, an error due to the miserasion of the preceding data can be selected easily and assuredly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error detection circuit used, for example, in a PCM recording/reproducing apparatus.

Background Art and Problems There has been proposed an apparatus for recording and reproducing PCM signals using, for example, a rotary head type tape recorder.

In this case, digital signals such as PCM signals are recorded in saturation, so when recording is performed again on the recorded tape, the previous signal is completely erased by the newly recorded signal, and a special erase head is used to erase the previous signal. There is no need to provide one.

However, in this case, if one tape is recorded with different devices, for example, the device labeled - will record as shown by the solid line in Figure 1, and the other devices will record as shown by the broken line due to a shift in the scanning position of the rotating head. A recording is made. Then, only the portion that overlaps with the solid broken line is erased, and when this is reproduced by the first - device, the previous signal and the subsequent signal are mixed and reproduced, as shown on the right side of the drawing.

Here, the PCM signal is generally provided with an error detection code such as CRC, but since the previous signal mentioned above is a correct signal, detection by CRC or the like is impossible. Therefore, this signal is supplied as correct data to a decoder circuit or the like, causing malfunction or destroying the original correct data.

Note that it is difficult to achieve complete compatibility with respect to the scanning position of the rotary head.

Additionally, if there is dust on the tape during re-recording, the above-mentioned unerased residue may occur, and when the dust is removed later, the previous data may be mixed in and played back. be.

OBJECTS OF THE INVENTION In view of these points, the present invention detects errors caused by previous data being erased and left behind.

SUMMARY OF THE INVENTION The present invention provides digital signals arranged and recorded in the width direction of a recording medium, and an index code indicating the recording of arbitrary six symbols for each block of a predetermined number of bits of the digital signal. An arbitrary above-mentioned index code in the widthwise central portion of the recording medium is detected, and this detected above-mentioned index code is compared with the above-mentioned index code in the reproduced block, and through this comparison, it is possible to detect an error in the above-mentioned block. This is an error detection circuit that performs detection, and according to this, it is possible to detect errors caused by unerased data and blanks of previous data.

Embodiment In FIG. 2, for each block of a predetermined number of bits of a digital (data) signal to be recorded, a synchronization signal S1 an index signal 11 an address signal A1 two different series of parity check codes P, Q, and a CRC check code C is provided. Here, the index signal I is set to a different value for each series of recording, and is set to the same value throughout the series of recordings.

Next, FIG. 3 shows the structure of the erroneous detection circuit. The above-mentioned signal is reproduced and supplied to the input terminal (1) in the figure.

This signal is supplied to the CRC detection circuit (2), and CRC error detection is performed. Furthermore, the data signal D in the signal
1 and 2 integrity check codes P and Q are supplied to the decoder (3).

Also, the index signal I part is taken out from the detection circuit (2), and this signal is held for one block period when no CRC error is detected, and this signal is supplied to the registers (4) and (5). be done. This register (4)
, (5), the synchronization circuit 00 supplies timings at two points spaced apart, for example, by about 4 blocks or more, in the widthwise center of the tape in accordance with the scanning of the rotary head, and the index signal 11. of this timing is supplied. I2 is stored in registers (4) and (5).

These two stored index signals 11 +I2 are compared in a comparison circuit (6), and when they match, the contents of the register (7) are rewritten with the index signal stored in the register (5), for example. Note that the register (7) is supplied with the timing at which the scanning of the rotary head is completed from the synchronization circuit αQ.

The index signal stored in this register (7) is supplied to a comparison circuit (8) and compared with the index signal from the detection circuit (2), and when they match, the signal is taken out.

This signal and a signal from the detection circuit (2) indicating that no error has been detected in the CRC are supplied to an AND circuit (9), and data is written in the decoder (3) based on the AND output.

Therefore, in this circuit, when two index signals match, it is detected that the index signal of that record is the same, and when they do not match, one is determined to be an error due to dust, etc., and the previous detected one is stored in the register (7). The index signal is maintained.

Note that errors due to dust etc. do not occur consecutively for four or more blocks.

Then, a data signal having an index signal matching this index signal is written to the decoder (3).

Erroneous data signals with different index signals caused by erased and unerased data are detected and eliminated.

Effects of the Invention According to the present invention, it has become possible to detect errors caused by unerased previous data.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of PCM recording and reproduction, Fig. 2 is an explanatory diagram of the present invention, and Fig. 3 is a configuration diagram of an example of the present invention◇ (1) is an input terminal, (2) is an CRC detection circuit, (3) a decoder, (4) and (5) index signal registers, (6). 'C8) is a comparison circuit, (7) is a detection signal register, D
I is a synchronous circuit.

Claims (1)

[Claims] The digital signals are arranged and recorded in the width direction of the recording medium, and an index code indicating the recording of any six rays is provided for each block of a predetermined number of bits of the digital signal, and an index code is provided at the center of the width direction of the recording medium. An error is made in which an arbitrary index code of the part is detected, the detected index code is compared with the index code in the reproduced block, and an error in the block is detected by this comparison. Detection circuit.