JPS6136307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal reproducing circuit for an audio device that records and reproduces audio information using pulse code modulation, and its purpose is to prevent the reproduction synchronization signal from being lost.

When using pulse code modulation to reproduce information such as audio or music recorded on magnetic tape, magnetic disks, or special recording materials (e.g. optical or thermal recording materials), a preset pulse train or pulse code modulation is used as a standard for signal processing. Synchronization signals based on synchronization patterns are used, but these can be broadly divided into cases where the synchronization signal is a certain pulse train, and cases where the synchronization signal is a pulse that is different from the audio and music information pulse amplitude. .

The present invention relates to the former case. In this type of device, when extracting a preset synchronization pulse train from an audio or music information pulse train, if there are any missing information such as scratches or dust on the recording material, it will not be possible to extract it as a synchronization pulse, and the reproduction signal processing This often causes malfunctions. Therefore, it is essential to prevent this synchronization signal from being lost. Hereinafter, the present invention regarding prevention of synchronization signal loss will be explained in detail with reference to the drawings.

Recording methods for recording and reproducing systems using pulse code modulation can be roughly divided into two types: one in which audio and music information is recorded in series, and one in which audio and music information is divided and recorded in parallel. Here, 1 for serial recording
An example is shown in FIG. In the signal configuration in this case, a synchronization signal and a check signal for detecting signal loss due to dust or scratches on the recording material are added every few sample data, and multiple writing using parity is employed. The sample data, synchronization signal, and error check code each consist of a few bits to about 16 bits. In FIG. 1, the synchronization signal is m bits, the sample data is n pieces, 1 sample is S bits, and the error check code is t bits.

FIG. 2a shows an example of synchronization signal extraction. A synchronizing signal pattern identical to the synchronizing signal pattern added during recording is prepared in advance, and a pulse is generated only when this pattern matches the reproduced signal pulse train. In FIG. 2a, 1 is a demodulator;
2 is a shift register, and 3 is a sign comparator. FIG. 2b shows how the synchronization signal is extracted. However, if there are scratches, dust, etc. on the recording material, the synchronization signal pattern will be exposed, resulting in no consistent output.

FIG. 3a is a block diagram of an embodiment of the present invention that achieves prevention of loss of reproduction synchronization signals. _A1 ,
A ₂ , A ₃ are counters, B ₁ , B ₂ are OR gates, C is an inverter, D is a synchronous signal extraction circuit, E ₁ , E ₂ , E ₃
is the preset terminal, F is the regeneration clock, G ₁ ,
G ₂ and G ₃ are carry signals, H is a load signal, I is a synchronization signal, and J is a normal synchronization signal. The operation of the circuit of the present invention will be explained below with reference to FIG. 3b.

In the example shown in Fig. 1, the part from the synchronization signal to the error check code consists of a total of (m + n × s + t) bits: m synchronization signal bits, sample data n × S bits, and error check code t bits. Appears in units. Furthermore, each bit is always synchronized with the reproduced clock. The synchronization signal generates one pulse when there is a pulse train that matches the m-bit synchronization pattern among the reproduced pulse trains. Thereafter, one pulse appears by repeating the above (m+n×S+t) bits.
However, in reality, synchronization signals may be lost due to scratches or dust on the recording material. In FIG. 3a, counters A ₁ , A ₂ , A ₃ are synchronized pattern generation period (m+
The α counter is preset to be slightly larger (longer) than n×S+t). When the synchronization signal pulse I is first generated from the synchronization signal extraction circuit D, one sets the counters A ₁ , A ₂ , and A ₃ to a preset state and starts counting α pulses, and the other outputs it as the synchronization signal J during that time. be done. If there is no missing synchronization signal, the above operation is repeated, but in this case, the counter carries up when it counts slightly more than the synchronization signal period (m+n×S+t) after inputting the load signal H due to synchronization signal I. pulse
Since it is configured to generate a carry pulse G ₃ , if a normal synchronization signal is repeated, the load signal H by the next synchronization signal counts α and the initial signal is generated again before generating a carry pulse G ₃ . The synchronizing signal extraction output I is obtained as the synchronizing signal J without any carry pulse.
However, if there is a loss of the synchronization signal, a carry pulse is generated by counting α times from the synchronization signal pulse I before the loss.
This signal is generated slightly later than the synchronization signal without _G3 and is output as the synchronization signal J.

The present invention is equipped with a counter that counts the number of clocks slightly larger than the number of clocks corresponding to the number of data bits between synchronization signals, and if the synchronization signal is extracted correctly during playback, the counter is reset by the synchronization signal. There is no output from this counter; on the other hand, when no synchronization signal is extracted, the counter is not reset and generates a count output pulse. Therefore, even if the synchronization signal is missing, the count output pulse can be used in place of the synchronization signal, making it possible to reproduce data continuously.

[Brief explanation of the drawing]

Figure 1 is an example of a signal configuration of a recording/reproducing device using pulse code modulation, Figure 2a is a block diagram of a synchronization signal extraction circuit, Figure 2b is a timing chart of the synchronization signal extraction circuit, and Figure 3a is a diagram of a synchronization signal extraction circuit. FIG. 3b is a block diagram of a synchronizing signal reproducing circuit according to an embodiment of the present invention, and FIG. 3b is a timing chart of the synchronizing signal reproducing circuit of the present invention. A ₁ , A ₂ , A ₃ ... Counter, B ₁ , B ₂ ... OR gate,
C... Inverter, D... Synchronous signal extraction circuit, E ₁ ,
E ₂ , E ₃ ... Preset terminal, F ... Regeneration clock,
G ₁ , G ₂ , G ₃ ...Carry signal, H...Load signal, I
...Synchronization signal, J...Synchronization signal.

Claims (1)

[Claims] 1. A synchronizing signal extracting means for extracting a synchronizing signal consisting of a predetermined pulse train, and counting the number of clocks slightly larger than the number of reproduced clocks corresponding to the number of data bits between the synchronizing signal and the next synchronizing signal. a counter that generates a count output pulse when counting up to the slightly larger number of clocks; and a first gate means that applies a reset pulse to the counter when either the synchronization signal or the count output pulse arrives; and second gate means for outputting either the synchronization signal or the count output pulse when it arrives, and when a correct synchronization signal is obtained from the synchronization signal extraction means, it is output through the second gate means. At the same time, the counter is reset by a reset pulse generated by the first gate means so that the first output pulse is not generated, and when the synchronization signal cannot be obtained from the synchronization signal extraction means, the counter is A synchronizing signal reproducing circuit for an audio device, characterized in that it is configured to output a generated count output pulse from a second gate means and to reset the counter by a reset pulse generated via the first gate means. .