SU1599895A1 - Device for cyclic clocking of digital data playback from magnetic record carrier - Google Patents

Abstract

The invention can be used in the reproduction of block-coded information, for example, in a system of noise-resistant coding of multi-channel magnetic recording equipment. The device contains an input data bus 1, a clock synchronization bus 2, a delay element 3, a shift register 4, a decoder 5 for the marker, a trigger 6, an AND 7 element, an OR element 8, an output sync signal bus 9, an output information bus 10, counters 11, 12 and triggers 13, 14, 15. The purpose of the invention is to reduce frame alignment by eliminating spurious marker signals and restoring frame synchronization pulses when a reproducible marker signals fall out. 2 Il.

Description

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The invention relates to instrumentation, in particular to a technique of magnetic recording, and can be used in a system for the noise-resistant coding of multi-channel digital magnetic recording apparatus.

The purpose of the invention is to reduce the error of cyclic synchronization of the reproduction of digital information.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing diagrams illustrating the principle of its action.

A device for cyclic synchronization of playback of block-coded digital information from a magnetic recording medium - magnetic tape contains an input bus 1 of reproduced digital information, an input bus 2 of a clock clock playback signal, a delay element 3, a shift register 4, a decoder 5 marker, the first trigger b, the And element 7, the element OR 8, the output bus 9 of the frame alignment signal, the output bus 10 of the reproduced digital information, the first 11 and second 12 pulse counters and the second 13, third 14 and fourth 15 trigger s.

The information bus 1 is connected to the information input of the shift register 4, the outputs of the bits of which are connected to the inputs of the decoder 5 of the marker, the output of which is connected to the first, informational input D of trigger b, the output of which is connected to the second input of the element 7, the output of which is connected to the first input element OR 8, the output of which is connected to the output bus 9 of the frame alignment signal and with the input of the binary counter 11 pulses set to the zero state. The output of the first bit of the shift register 4 is additionally connected to the output information bus 10.

The clock synchronization bus 2 is connected to the third inverse t input input t)) igger bis input of the delay element 3, the output of which is connected to the clock input of the shift register 4, with the second clock input of trigger b, with the counting input of the pulse counter 11 , with the third, inverse installation into the zero state of the trigger input 15 and with the third, inverse installation into the zero state of the trigger input 14, the output of which is connected to the second, installation in one state input of the trigger. 13.

The output of the fifth bit of the pulse counter 11 is connected to the first clocking input C of the trigger 14 and to the first clocking input C of the trigger 13, the inverse output of which is connected to the counting input of the binary counter 12 pulses, the output of the second bit of which is connected to the first information input D Trig

Hera 13, the direct output of which is connected to the first input of the element And 7.

The output of the sixth bit of the counter 11 pulses is connected to the second, clocking 5th input C of the trigger 15. The output of the ninth bit of the counter 11 pulses is connected to the second, informational input D of the trigger 14 and to the third, informational input D of the trigger 15, the output of which is connected to the second element input

 OR 8. The output of the element And 7 is connected

additionally with set to zero

the state of the input of the counter 12 pulses.

The device works as follows.

The feed to the bus 1 reproduces the digital information. The structure information consists of a sequence of frames, each of which contains, in particular, a 256-bit information block, a 16-bit control balance of the cyclic control code and a 16-bit marker combination

With the help of a clock signal arriving on bus 2, information in register 4 is advanced and triggers are set to the zero state, b, 14, 15.

5 Clock pulses are counted by counter 11. Each time, when a marker combination of the reproduced signal is inserted into the register 4 at the output of the decoder 5, diagram 1, FIG. 2) a signal is generated - a marker pulse. This signal records 0 with the front of the next clock pulse, trigger три, which is reset to its original zero state through a half-cycle negative half-wave clock signal. As a result, the output of trigger b (figure 2, fig. 2). With a duration of half-time, a positive pulse of a marker is generated5 that occurs through the element AND 7, the element OR8, and arrives at the output bus of the frame alignment signal, thereby realized by the marker's pulses.

The error of cyclic synchronization of the reproduction of digital information carried out with the help of markers recorded on magnetic media at the boundaries of frames (information blocks),

5 is determined by three features of this synchronization method: if the replay of the marker combination fails, a frame synchronization pulse will not be generated; with appropriate faults in the information block of the frame, a false pulse of the frame marker can be generated in a different location from the true one (the second pulse in diagram 2, fig. 2); a false pulse of the marker can also be formed when a frame of information bit combination coinciding with the marker appears in the information block. To protect against spurious signals (the second pulse in diagram 1, fig. 2) of the marker in the device, element And 7 is opened for passing the output signal of trigger 6 only in the region of the expected appearance of the marker pulse. The element AND 1 is opened by the output signal of the trigger 13 shown in diagram 3, fig. 2

The length of the time gate (time window) of the expected passage of the reproduced marker signal in the proposed device is, in particular, ± 16 cycles.

To protect the marker signals from falling out (shown by a dotted line in the second half of diagram 1, fig. 2), the device generates a continuous signal for replacing marker pulses, which from the output of the trigger 15 (diagram 7, fig. 2) goes to the output bus 9 through the OR element eight.

From the output element OR 8, the marker's output pulse sets the counter 11 to the zero state. And the counter 12 sets the output pulse of the element marker AND 7 to the zero state. After 256 cycles thereafter, i.e. after the end of the frame information block on the information inputs of the flip-flops 14 and 15 establish a high level of voltage generated at the output of the ninth discharge (diagram 6, fig. 2) of the counter 11.

After 16 cycles thereafter, the trigger 14 switches to one state and its signal sets to one state the trigger 13, at the output of which there are positive pulses in diagram 3, Fig. 2) a “gate” signal is generated, the opening element AND 7. The signal at the inverse of the output of the trigger 13 is shown in diagram 4, fig. 2

After 32 cycles, after the occurrence of a high voltage level at the output of the ninth discharge of counter 11 and, accordingly, 16 cycles after the formation of the enable signal at the gate at the output of the trigger 13, a signal is generated at the output of the trigger 15 (chart 7, fig. 2) which, in half a clock cycle, is reset by a clock signal to its original state. As a result, at the output of the trigger 15, a pulse of replacing the reproduced signal of the marker forms a half-cycle duration. The substitution pulse coincides in time with the reproduced pulse of the marker when it comes from the output of the element And 7 at the proper moment.

At the output of the trigger 14, a pulse is also formed with a duration of half a cycle.

After 16 cycles after the formation of the replacement pulse, the trigger 13 is set to the zero state and the element 7 is locked. The positive voltage level generated at the same time at the inverse output of the trigger 13 (diagram 4 of Fig. 2) is counted by a counter of 12 cycles.

If the next, regular impulse marker at the output of the element And 7 is not formed, then the trigger 13 will be formed allowing "the gate for the element I7; to the output bus 9, a pulse of replacing the signal of the marker from the output of the trigger 15; Counter 12 will calculate the second cycle and a high voltage level will be generated at its output (Figure 5, Fig. 2).

If the next element does not arrive at AND 7, i.e. a second pulse of the reproduced marker, then in the same way an output bus 9 will receive a replacement pulse of the reproduced marker signal and an enabling signal will be generated at the output of trigger 13. But the signal is no longer removed after 32 cycles (the second positive pulse in diagram 5, fig. 2), and element 7 will be constantly open before the reproduction of the marker signal. Removing the gate, in the particular case after a two-time absence of reproduction of the marker, is necessary for putting the device into synchronism both at the initial moment of its operation and in the case of a large reproduction error.

Element 3 maintains the moment of recording information in trigger 6 regarding the removal of the signal at its installation input.

The front of the frame alignment pulse on the output bus 9 corresponds to the beginning of the first bit of the frame information block on the output bus 10.

Claims (1)

Invention Formula Cyclic synchronization device for reproducing digital information from a magnetic recording medium containing a clock synchronization bus, serially connected information bus, shift register, marker decoder, and first trigger, serially connected information bus, shift register, marker decoder and first trigger, serially connected element I, element OR and frame alignment output bus, first and second pulse counters, second and third triggers, and a delay element, so that, in order to reduce the cyclic synchronization error, a fourth trigger is inserted in it, connected to the two outputs of the first impulse counter and connected to the second input of the OR element, the output of which is additionally connected to the installation input of the first pulse counter, the third output of which connected to the first inputs of the second and third flip-flops, the output of the last of which is connected to the second input of the second trigger, the output connected to the first input of the And element, the output of which is additionally connected with the installation input of the second pulse counter, the counting input and the output of which are connected respectively to the inverse output and the third input of the second trigger, while the second input of the third trigger connected to one of the outputs of the first pulse counter, and the clock input of the shift register, the counting input of the first pulse counter, the second input of the first trigger and the third inputs of the third and fourth triggers are connected to the output of the delay element whose input is connected to the clock synchronization bus and to the third input of the first trigger output connected to the second input element I.