JPH0343814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data synchronization circuit for PCM signals.

As a circuit for extracting data words from a PCM signal in which a frame synchronization signal is attached to each of multiple data words, the circuit reproduces a clock synchronized with each bit of serial data and extracts the '1' and '0' of the PCM signal.
A bit synchronization circuit that determines the signal and captures the signal.
A frame synchronization signal is extracted from a PCM signal, and a data synchronization signal synchronized with a data word is generated from the extracted frame synchronization signal and bit synchronization signal. I filed an application (patent application 1982-
No. 153700, patent application No. 153705). The generation of the bit synchronization signal in this application is from '0' to '1' in the PCM signal.
Alternatively, when extracting the transition point from '1' to '0', that is, the signal edge, and using this edge signal to synchronize the phase of the asynchronous circuit and generate the bit synchronization signal, errors caused by jitter, dropout, etc. The present invention relates to a method for removing timing edges.

As a method to remove edges with incorrect timing, the edge interval of the signal is detected by pattern matching using a shift register or by counting clock pulses by a counting circuit, and the signal edges with the edge interval allowed by the signal format are used for phase synchronization. This method is used as an edge. This method reduces data word capture errors due to the jitter, dropout, and the like.

However, on the other hand, the ability to extract frame synchronization signals is reduced. This detects a frame synchronization signal pattern using a bit synchronization pulse for data acquisition. In this method, when the signal pattern is degraded due to jitter or dropout before the frame synchronization signal, it is not detected as a correct pattern, making it impossible to remove edges for phase synchronization. In this case, the timing of the bit synchronization pulse is shifted due to jitter or uneven rotation of a recording medium such as a disk, resulting in erroneous detection of the synchronization signal pattern. Therefore, no frame synchronization signal is detected. Generally, if a frame sync signal is not detected, pulses are supplemented from a previously detected frame sync signal. However, due to uneven rotation of the disk, it is not possible to replenish the frame synchronization signal at the correct timing. Therefore, the data string after the supplemented frame synchronization signal cannot be captured in the correct order, and 1
All data within the frame will be captured as error data. Such error propagation occurs. In this way, if the frame synchronization signal cannot be detected, it will result in a data error of one frame, so it is desirable that the detection ability be as high as possible. On the other hand, for data, only the data itself becomes an error, and there is no error propagation over one frame, as in the case of a frame synchronization signal. That is, while a bit synchronization pulse generation method in which phase synchronization is achieved using edges of a correct pattern in a signal is effective for bit synchronization of data, no consideration has been given to extracting a frame synchronization signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data synchronization circuit that eliminates the drawbacks of the prior art described above and improves the ability to extract frame synchronization signals.

Therefore, in the present invention, the frame synchronization signal pattern extraction circuit and the bit synchronization pulse generation circuit of the data synchronization circuit are separated and provided for exclusive use. As a result, both the circuits use a suitable system, so that the frame synchronization signal pattern extraction ability and the data synchronization circuit extraction ability can be improved independently of each other. That is, by capturing data with the first bit synchronization pulse generation circuit synchronized with the edges of the signal pattern within the permissible range of the transmission rate of the reproduced digital signal, errors in data word capture due to jitter, dropout, etc. are reduced. On the other hand, by detecting frame synchronization signals with the second bit synchronization pulse generation circuit that is synchronized with all edge signals that are signal patterns outside the permissible range of the transmission rate, it is possible to prevent edges for phase synchronization from being lost. , the ability to extract frame synchronization signals increases.

In explaining the present invention, a specific example will be described in which the present invention is used in a compact disc (hereinafter referred to as CD) type digital audio disc player.

First, FIG. 1 shows an example of the configuration of a CD system PCM playback signal format. This will be explained below with reference to the same figure.

FIG. 1a is a waveform diagram showing the structure of a reproduced signal pattern, and the numbers in the diagram represent the number of bits. In the same figure, b is a bit synchronization signal, c is an example of an extracted frame synchronization signal,
d indicates a symbol synchronization pulse (hereinafter referred to as data synchronization pulse).

Here, c is an example of extraction when the frame synchronization signal pattern is determined using the first 22 bits of the frame synchronization signal pattern composed of 24 bits. One frame consists of 588 bits. This one frame consists of a 24-bit frame synchronization signal, one control display symbol consisting of 14 bits, 24 data symbols, and 8 parity symbols, for a total of 33 symbols, and 34 margin bits consisting of 3 bits. has been done.

In order to extract each symbol (hereinafter referred to as data), first a bit synchronization signal is generated to determine '1' or '0' of the reproduced signal (hereinafter referred to as EFM signal), and then the same EFM signal is A frame synchronization signal is extracted from the frame synchronization signal, and a data synchronization pulse is generated from the extracted frame synchronization signal and bit synchronization signal or from the frame synchronization signal, bit synchronization signal, and EFM signal. For example, data words are separated every 17 times from the frame synchronization signal extracted in FIG. 1c to the bit synchronization signal in FIG. 1b. Therefore, the first
The signal in Figure d can be used as a data synchronization pulse. This data synchronization pulse synchronizes the EFM signal taken in by the bit synchronization pulse and data is taken in.

FIG. 2 shows a block configuration of an embodiment of the data synchronization circuit of the present invention. The operation will be explained below with reference to the figures. A bit synchronization pulse 7 is generated from the EFM signal 6 by a bit synchronization pulse generation circuit 1. This bit synchronization pulse causes the EFM signal 6 to become '1' or '0'.
are determined and sequentially taken into the shift register 3. The number of stages of this shift register is at least the number of bits constituting one data word or the number of constituting bits required for extracting a frame synchronization signal, whichever is greater. Bit synchronization signal extraction pulse 13 is generated from EFM signal 6 by bit synchronization signal extraction pulse generation circuit 12.
A frame synchronization signal is detected by a frame synchronization signal detection circuit 4 using the EFM signal 6 and a bit synchronization signal extraction pulse 13, and a frame synchronization pulse 8 is generated. A data synchronization pulse 11 is generated from the data synchronization pulse generation circuit 2 using the frame synchronization pulse 8, the bit synchronization pulse 7, and the EFM signal 6. The data latch circuit 5 takes in the shift register parallel output 9 with a data synchronization pulse 11 and obtains a latch output 10. Here, in the bit synchronization pulse generation circuit 1, the EFM signal 6 changes from '0' to '1' or '
The point of change from 1' to '0', that is, the edge, is extracted, phase synchronization is achieved using this edge, and bit synchronization pulse 7 is generated. Here, the phase synchronization method includes a method using a PLL and a method using an asynchronous synchronization circuit. In order to prevent phase synchronization errors caused by erroneous edges caused by dropouts of the EFM signal 6, noise, jitter, etc., correct edges are selected. Extract and perform phase synchronization.

In addition, in detecting a frame synchronization signal pattern, a method is employed in which the bit synchronization signal extraction pulse generation circuit 12 and the frame synchronization signal detection circuit 4 phase-synchronize all signal edges that are not affected by disturbances other than the frame synchronization signal, or The frame synchronization signal detection margin can be increased by using a method of counting signal edge intervals.

Here, bit synchronization signal extraction pulse generation circuit 1
2 and the synchronization signal detection circuit 4 are provided with a frame pattern matching circuit for frame synchronization signal extraction, which has the same configuration as the bit synchronization pulse generation circuit 1 and the shift register 3. FIG. 3 shows an embodiment of a circuit in which the frame synchronization signal can be detected by using this method, and the circuit configuration is further simplified.

Figure 3 shows the bit synchronization signal extraction pulse generation circuit 1.
A more detailed embodiment of the two-frame synchronization signal detection circuit 4 and the data synchronization pulse generation circuit 2 will be shown.
This will be explained below with reference to the figures.

EFM6 is input to two stages of shift registers 14-1 and 14-2. This shift register 14
-1's output 18 and 14-2's output are E-OR
Bit synchronization signal extraction pulse 13 input to circuit 15
Output. Here, the shift registers 14-1 and 2 use the output 17 of the oscillation circuit 16 as a shift clock. Therefore, the pulse width of the bit synchronization signal extraction pulse 13 is equal to the period of the output 17. Here, the period of the output 17 of the oscillation circuit 16 is set to, for example, 1/8 of the EFM signal period, about 28.9 nS. Next, the frame synchronization signal detection circuit 4 receives the bit synchronization signal extraction pulse 13 and determines whether the signal is a frame synchronization signal or not.

To make this determination, the interval of the bit synchronization signal extraction pulse 13 is counted, the counter is reset with the extraction pulse 13 for extracting the edge intervals 11T and 11T of the frame synchronization signal pattern, and the counter counts the clock pulse 20 of the oscillation circuit 19. A circuit 21 is provided, and the output 22 of each stage of the counter 21 is sent to a decoder 2.
Decode with 3. Here, the decoder 23 outputs the decode output 24 when the time corresponds to 11T.
By setting the decode value to 1, 11T in the frame synchronization signal pattern is detected. This decoded output 24 is extracted as pulse 13
11.
If T is detected twice consecutively, a frame synchronization detection output 26 is output. This output 26 and EFM
Data synchronization pulse 11 from signal and bit synchronization signal
Extract.

FIG. 4 shows a more detailed embodiment of the bit synchronization pulse generation circuit 1, shift register 3 and data latch 5. This will be explained below with reference to the figures.

2-stage shift register 28, 29 for EFM signal 6
The shift register outputs 31 and 32 are input to an edge detection circuit 30 to generate an edge output 38. Here, the edge detection circuit 30 is an E-OR with shift register outputs 31 and 32 as input.
Consists of gates.

This edge output 38 is input to the phase synchronization circuit 3.
4 generates a bit synchronization pulse 7. Here, as the phase synchronization circuit 34, a tank circuit, a PLL circuit, an asynchronous synchronization circuit, etc. are used. For example, when an asynchronous synchronization circuit is used, a correct edge output is extracted from the edge output 38, and the extracted edge performs asynchronous synchronization using the output clock 35 of the oscillation circuit 33. The output clock 35 is also used as a shift clock for the shift registers 28 and 29.

Bit synchronization pulse 7 generated as above
as the shift clock of shift register 36
Capture EFM signal 6. Here, the number of stages of the shift register 36 is, for example, 14 stages, which is equal to the number of bits in one word. This shift register parallel output 9 is taken into the data latch 37 by a data synchronization pulse 11, the serial data is converted into parallel data, and a latch output 10 which is a parallel data output is generated. Here, the number of stages of the data latch 37 is, for example, 14 stages, which is equal to the number of stages of the shift register.

In Fig. 4, shift register 3 takes in EFM signal 6 as an input signal to shift register 36, but in actual CD format,
The EFM signal was converted to NRZI and recorded. Therefore, it is necessary to input the reproduced EFM signal 6 after inverse NRZI conversion. This inverse conversion circuit has a configuration of shift registers 14-1, 2 and E-OR gate 15 in FIG.
This can be done by using the same clock as clock 7 of shift register 36 in FIG. 4 as the clock. In this case, the signal is shifted by two clocks, so
Data synchronization pulse 11 also needs to be shifted by two clocks.

FIG. 5 shows a more detailed circuit diagram of a portion of the phase synchronization circuit 34 excluding the correct pattern edge detection circuit. J.K-F.F44, 39 and 4
0 is preset by edge output 38 and both output clock pulses 35 of 2-input AND gate 42
A 3-bit counting circuit is constructed to count. This 3
The bit counting circuit output is decoded by a 3-input AND gate 43, and the decoded output is sent to D-F・F41.
latches and generates a bit synchronization pulse 7.

The operation shown in FIG. 5 will be explained in more detail with reference to the timing chart shown in FIG. Figure 6a shows the output clock pulse 35, Figure 6b shows the edge output 38,
The figure c shows the Q output of J.K-F.F44, the figure d shows the Q output of J.K-F.F39, and the figure e shows the J.K-
The Q output of the F.F.40, f in the figure represents the output of the 3-input AND gate 43, and g in the same figure represents the Q output of the D-F.F41. Here, the edge output 38 in FIG. 6b is an example in which the edge interval is ten times the period of the output clock pulse 35. Further, the output, ie, the decoded value, of the 3-input AND gate 43 in FIG.
This is an example in which the output timing is set to the fourth clock of the output clock pulse 35 from the signal edge. The dashed line in FIG. 6b shows the case of correct timing for one cycle of the signal bit rate.

FIG. 7 shows a more detailed circuit diagram of a portion of the counter circuit 21, decoder 23, and frame synchronization pattern detection section 25. The operation will be explained below with reference to the figures. J, K-F, F45, 46 and 47 are preset by bit synchronization signal extraction pulse 13 and 2
This is a counter that counts cross pulses 20 constituted by an input AND gate 48. A decoded output 24 is obtained by a decoder 23 which matches the output of this counter circuit 21 with a 3-input AND gate 49 and latches it with DF.F50. This decode output 24 gates the bit synchronization signal extraction pulse 13 to obtain a frame synchronization signal gate output 52.

The above operation will be explained using the time chart shown in FIG.

8a shows the clock pulse 20, b shows the bit synchronization signal extraction pulse 13, c, d, and e show the outputs of J.K-F.F45, 46 and 47, and f shows the output of D-F.F50. output, that is, decode output 2
4, and g in the figure represents the output of the two-input AND gate 51. When the bit synchronization signal extraction pulse b has a predetermined period, that is, eight times the period of the clock pulse 20, it matches the decode output 24 and the output of the two-input AND gate 51 is output. In contrast, the figure b
If the interval between the bit synchronization signal extraction pulses b is shorter or longer than the predetermined period, as shown by the broken line in FIG.

To simplify the explanation above, the decoded value was set to have a cycle eight times that of the clock pulse 20, but the frame synchronization signal pattern of the CD system has a bit rate of T.
It is composed of 11T, 11T, and 2T patterns, and the decode value is set to the same pattern length. For this purpose, the edge interval is 11T, so the counter circuit 21 is constituted by seven stages of J.K.F.F., and the decoder 23 is set to a decode value of 88. Further, although not mentioned in the description of the decoder 23, it is possible to widen the synchronization signal extraction margin by providing a margin for the decoded value. Furthermore, the explanation using the time charts in FIGS. 7 and 8 also applies to a circuit that extracts only the edges of the correct pattern from among the signal edges from the edge output 38 of the edge detection circuit 30 in the phase synchronization circuit 34 of FIG. Applied.

According to the present invention, since all edge signals are used to extract the frame synchronization signal pattern, there are no problems such as loss of phase synchronization or the time required for acquisition, unlike with bit synchronization pulses for data acquisition, and the input It is possible to extract patterns for each signal edge, and the extraction margin can be widened.For data extraction, the bit strobe pulse generated by the correct signal edge is used to determine whether the signal is '1' or '0', and data synchronization is performed. can be achieved. Furthermore, in a CD player, the rotation of a disk motor is controlled by a frame synchronization signal. Therefore, the data synchronization circuit according to the present invention has the effect of widening the rotation control range of the disk motor by widening the frame synchronization signal extraction margin.

[Brief explanation of drawings]

Figure 1 is a signal configuration diagram of CD format, Figure 2
3 is a circuit diagram showing a more detailed embodiment of the bit synchronization circuit 12 and the data synchronization circuit 2, and FIG. 4 is a circuit diagram showing an embodiment of the data synchronization circuit according to the present invention. A circuit configuration diagram showing a more detailed embodiment of the pulse generation circuit 1, shift register 3, and data latch 5, FIG. 5 is a detailed circuit diagram of the phase synchronization circuit, and FIG. 6 is a timing chart showing the operation of the phase synchronization circuit. FIG. 7 is a detailed circuit diagram of the counter circuit, decoder, and frame synchronization pattern detection section, and FIG. 8 is a timing chart showing the operation of the counter circuit, decoder, and frame synchronization pattern detection section. 1: Bit synchronization pulse generation circuit, 2: Data synchronization pulse generation circuit, 3: Shift generator,
4: Frame synchronization signal detection circuit, 5: Data latch, 6: EFM signal, 7: Bit synchronization pulse,
8: Synchronous pulse, 9: Shift register parallel output,
10: Data latch output, 11: Data synchronization pulse.

Claims (1)

[Scope of Claims] 1. The above bit synchronization is achieved by generating a bit synchronization pulse synchronized with a reproduced digital signal extracted from a recording medium on which a digital signal is recorded in a frame configuration in which a frame synchronization signal is provided for each of a plurality of data words. a first bit synchronization pulse generation step for generating a first bit synchronization pulse synchronized with an edge of a signal pattern within a permissible range of a transmission rate of a reproduced digital signal in a data synchronization circuit that takes in the plurality of data words by means of a pulse; with the circuit. a data capture circuit that captures a data word based on the first bit synchronization pulse; and a second bit synchronization pulse that generates a second bit synchronization pulse that is synchronized to edges of the signal pattern that are outside the tolerance range of the transmission rate. A data synchronization circuit comprising: a synchronization pulse generation circuit; and a frame synchronization signal detection circuit that detects a frame synchronization signal based on the second bit synchronization pulse. 2 The first bit synchronization pulse generation circuit detects the edge of the correct signal pattern in the reproduced digital signal and generates a bit synchronization pulse, and the second bit synchronization pulse generation circuit 2. The data synchronization circuit of claim 1, wherein all edges of the signal are used to generate the bit synchronization pulse.