JP3956525B2 - Sync signal detection protection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sync signal detection protection circuit used in an information reproducing apparatus for reproducing information recorded on a disc such as a CD (compact disc) or a DVD (Digital Versatile Disc), and more particularly to a reproduced digital signal. When the synchronization signal included in the data is detected and the synchronization signal is lost, the synchronization signal can be interpolated (supplemented).
[0002]
[Prior art]
Conventionally, in the case of a CD, for example, digital data is arranged in a frame in a predetermined format modulated by EFM (Eight to Fourteen Modulation) and recorded on a disc. One frame includes a frame synchronization signal arranged at the head, a plurality of audio information words, an error correction word, and the like, and is composed of 588 channel bits as a whole.
[0003]
Among these, the frame synchronization signal is composed of 24 channel bits, and has a specific pattern so that it can be distinguished from other information. The frame synchronization signal is used for dividing a frame when reproducing audio information, and is also used for generating a data separation signal for dividing data in a frame by a predetermined unit. Is done.
[0004]
For this reason, the reproducing apparatus for reproducing the CD is provided with a synchronizing signal detection circuit for detecting a frame synchronizing signal from the reproduced digital data. Further, in the above reproducing apparatus, when a frame synchronization signal is lost due to, for example, a dropout caused by a scratch on the disk, a synchronization signal protection circuit for interpolating the lost frame synchronization signal is provided. It is used in combination with the above sync signal detection circuit.
[0005]
FIG. 5 shows an example of the configuration of a conventional synchronization signal detection protection circuit.
[0006]
The synchronization signal detection protection circuit includes a synchronization signal detection circuit 1, an AND circuit 2, an OR circuit 3, a channel bit counter 4, a window generation circuit 5, an interpolation number counter 6, and an OR circuit 7. The synchronization signal detection circuit 1 receives an NRZ signal obtained by converting the EFM signal by the signal conversion circuit 8. Further, the PLL circuit 9 generates a clock signal PLCK from the EFM signal, and each circuit is operated by the clock signal PLCK.
[0007]
Next, the operation of the conventional synchronization signal detection protection circuit having such a configuration will be described with reference to the time chart of FIG.
[0008]
Now, at time t1 shown in FIG. 6, when the synchronization signal detection circuit 1 detects the synchronization signal SYNC as shown in FIG. 6B, the window signal from the OR circuit 7 at this time is as shown in FIG. 6C. “H” level. For this reason, the synchronization signal SYNC is extracted as a normal synchronization signal DTSYNC by the AND circuit 2 and then extracted as the synchronization signal DTIPSYNC by the OR circuit 3 and supplied to the channel bit counter 4.
[0009]
The channel bit counter 4 performs a counting operation based on the synchronization signal DTIPSYNC from the OR circuit 3, outputs the count value (count value) to the window generation circuit 5, and at the time when the count value reaches a predetermined value. The synchronization signal IPSYNC for interpolation as shown in FIG. 6 (E) is output to the OR circuit 3. The window generation circuit 5 generates a window signal WIN0 as shown in FIG. 6G based on the count value from the channel bit counter 4, and outputs it to the interpolation number counter 6 and the OR circuit 7, respectively.
[0010]
If the synchronization signal detection circuit 1 does not detect the synchronization signal SYNC at time t2, the AND circuit 2 does not output the normal synchronization signal DTSYNC. However, as shown in FIG. 6E, the synchronization signal IPSYNC for interpolation is output from the channel bit counter 4 and is input to the OR circuit 3, so that the OR circuit 3 receives the synchronization signal IPSYNC. An interpolated synchronization signal DTIPSYNC is output (see FIG. 6F). At this time, since the normal synchronization signal DTSYNC was not obtained from the AND circuit 2, the fact is counted by the interpolation number counter 6, and the counted value is “1” as shown in FIG. Become.
[0011]
When the synchronization signal detection circuit 1 cannot detect the synchronization signal SYNC again at time t3, the OR circuit 3 outputs the synchronization signal DTIPSYNC interpolated by interpolation of the synchronization signal IPSYNC from the channel bit counter 4 Is done. At this time, the count value of the interpolation number counter 6 is “2” as shown in FIG. 6 (H), and the window signal WIN1 output from the interpolation counter 6 during the period when the count value is “2”. 6 becomes “H” level as shown in FIG. 6 (I), and the window signal output from the OR circuit 7 also becomes “H” level as shown in FIG. 6 (C). The number of consecutive undetected times is 2 in this example, but any number is possible.
[0012]
Further, when the synchronization signal detection circuit 1 detects the synchronization signal SYNC at time t4 as shown in FIG. 6B, the window signal output from the OR circuit 7 at this time is at the “H” level. The signal SYNC is extracted by the AND circuit 2 as a normal synchronization signal DTSYNC. At this time, the interpolation counter 6 is initialized by the synchronization signal DTSYNC, and the window signal WIN1 output from the interpolation counter 6 to the OR circuit 7 is “H” as shown in FIG. The window signal output from the OR circuit 7 also changes from the “H” level to the “L” level as shown in FIG. 6C.
[0013]
Thus, in the conventional circuit of FIG. 5, after the synchronization signal detection circuit 1 could not detect the synchronization signal SYNC at times t2 and t3, the synchronization signal detection circuit 1 could detect the synchronization signal SYNC first at time t4. Sometimes, the synchronization signal SYNC detected first is treated as a regular one. For this reason, when the synchronization signal SYNC detected first is incorrect, there is an inconvenience that it lacks reliability and is unsuitable for practical use.
[0014]
Therefore, a circuit shown in FIG. 7 is known as a synchronization signal detection protection circuit for solving such inconvenience.
[0015]
The conventional circuit shown in FIG. 7 differs from the conventional circuit shown in FIG. 5 in that the channel bit counter 4 and the window generation circuit 5 of the circuit shown in FIG. 5 are replaced with a main channel bit counter 4A and a main window generation circuit 5A. A subchannel bit counter 10, a subwindow generation circuit 11, and a logic circuit 12 are added. The logic circuit 12 is composed of two AND circuits 121 and 122 and an OR circuit 123.
[0016]
The operation of the synchronization signal detection protection circuit having such a configuration will be described with reference to the time chart of FIG.
[0017]
Now, at time t1 shown in FIG. 8, when the synchronization signal detection circuit 1 detects the synchronization signal SYNC, the main window signal from the OR circuit 7 is at "H" level as shown in FIG. This is input to the AND circuit 2 through the logic circuit 12. For this reason, the synchronization signal SYNC is extracted as the normal synchronization signal DTSYNC by the AND circuit 2 and then extracted as the synchronization signal DTIPSYNC by the OR circuit 3 and output to the main channel bit counter 4A.
[0018]
If the synchronization signal detection circuit 1 does not detect the synchronization signal SYNC at time t2, the AND circuit 2 does not output the normal synchronization signal DTSYNC. However, the synchronization signal IPSYNC for interpolation is output from the main channel bit counter 4A and is input to the OR circuit 3, so that the synchronization signal IPSYNC is interpolated and interpolated from the OR circuit 3 DTIPSYNC is output. At this time, since the normal synchronization signal DTSYNC was not obtained from the AND circuit 2, the fact is counted by the interpolation number counter 6, and the counted value is “1” as shown in FIG. Become.
[0019]
When the synchronization signal detection circuit 1 cannot detect the synchronization signal SYNC again at time t3, the synchronization signal IPSYNC from the main channel bit counter 4A is interpolated from the output of the OR circuit 3 and interpolated. DTIPSYNC is output. At this time, the count value of the interpolation counter 6 is “2”, and the window signal WIN1 output from the interpolation counter 6 is as shown in FIG. At this time, the main window signal of the OR circuit 7 also becomes the “H” level as shown in FIG. This is also an example when it is assumed that the number of consecutive undetected times is two as in the conventional circuit.
[0020]
When the synchronization signal detection circuit 1 detects the synchronization signal SYNC at time t4, the window signal WIN1 from the interpolation number counter 6 at this time is at "H" level as shown in FIG. The bit counter 4A starts counting and outputs the counted value to the sub window generating circuit 11. The sub window generation circuit 11 outputs a sub window signal as shown in FIG. 8J during the period before and after the count value reaches a predetermined value, and outputs this sub window signal to the AND circuit 122. At time t4, since the gate signal of the AND circuit 2 is in the “L” level, the synchronization signal SYNC detected by the synchronization signal detection circuit 1 is not extracted from the AND circuit 2 as the normal synchronization signal DTSYNC.
[0021]
When the synchronization signal detection circuit 1 detects the synchronization signal SYNC again at time t5, the subchannel bit counter 4A starts counting and the synchronization detected by the synchronization signal detection circuit 1 as in the case of time t4. The signal SYNC is not extracted from the AND circuit 2 as the normal synchronization signal DTSYNC.
[0022]
At time t6, when the synchronization signal detection circuit 1 further detects the synchronization signal SYNC as shown in FIG. 8B, at this time, the subwindow signal output from the subwindow generation circuit 11 is at the “H” level. As a result, the gate signal of the AND circuit 2 becomes “H” level. For this reason, the synchronization signal SYNC detected by the synchronization signal detection circuit 1 is extracted by the AND circuit 2 as a normal synchronization signal DTSYNC.
[0023]
Further, at time t6, the interpolation number counter 6 is initialized by the synchronization signal DTSYNC, and the window signal WIN1 output from the interpolation number counter 6 to the OR circuit 7 is shown in FIG. Simultaneously with the change from the “H” level to the “L” level, the main window signal output from the OR circuit 7 also changes from the “H” level to the “L” level as shown in FIG.
[0024]
[Problems to be solved by the invention]
As described above, in the conventional circuit of FIG. 7, after the synchronization signal detection circuit 1 cannot detect the synchronization signal SYNC continuously for a predetermined number of times (in the above example, twice), the synchronization signal is detected at time t4 and time t5. Even if the detection circuit 1 can detect the synchronization signal SYNC twice, the synchronization signal is not treated as a regular one, but only when the synchronization signal is detected at time t6 after a predetermined period from time t5. The sync signal was handled as a regular one. For this reason, there is an advantage that reliability can be ensured when the synchronization signal SYNC is detected, but there is an inconvenience that wasteful time is required until resynchronization.
[0025]
Further, in the conventional circuit of FIG. 7, since the subchannel bit counter 10, the sub window generation circuit 11, and the logic circuit 12 are added to the conventional circuit of FIG. 5, the circuit scale is increased and the configuration is complicated. There is an inconvenience of becoming.
[0026]
Therefore, in view of the above points, an object of the present invention is to detect a synchronization signal that can reduce the time until the resynchronization while ensuring the reliability of the resynchronization and can reduce the circuit scale. A protection method and a detection protection circuit thereof are provided.
[0027]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, each invention described in claim 1 and claim 2 is configured as follows.
[0028]
That is, the invention according to claim 1 is a synchronization signal detecting means for detecting the synchronization signal from digital data including the synchronization signal for each frame, and a synchronization signal for extracting the detected synchronization signal based on its periodicity. If the synchronization signal is not detected by the extraction means and the synchronization signal detection means, the synchronization signal interpolation means for interpolating the synchronization signal, and the synchronization signal detection means cannot detect the synchronization signal, In a synchronization signal detection protection circuit comprising a counting means for obtaining the number of times the detection is impossible, the synchronization signal extracting means is capable of extracting the synchronization signal when the count value of the counting means reaches a first predetermined value. When a synchronization signal is detected in this state, the synchronization signal is estimated as a normal synchronization signal and extracted by the synchronization signal extraction unit and then counted by the counting unit. When the synchronization signal is detected without setting the second predetermined value and the count value of the counting means reaches the first predetermined value, the synchronization signal is extracted and the previously detected synchronization signal is normalized. And a control means for controlling to initialize the count value of the counting means.
[0029]
Further, the invention according to claim 2 is the synchronization signal detection protection circuit according to claim 1, wherein the second predetermined value to which the counting means is set is obtained by subtracting 1 from the count value immediately before the set. Value.
[0031]
As described above, in the present invention, when the synchronization signal is not continuously detected a predetermined number of times, the synchronization signal detected thereafter is estimated and extracted as a normal synchronization signal. When it is detected again after the lapse of a predetermined period, the synchronization signal is extracted and the previously detected synchronization signal is determined as a normal synchronization signal. For this reason, while ensuring the resynchronization reliability, the time until the resynchronization can be shortened, and the circuit scale can be reduced.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0033]
FIG. 1 is a block diagram showing a configuration of an embodiment of a detection protection circuit for a synchronous circuit according to the present invention.
[0034]
As shown in FIG. 1, the detection protection circuit of the synchronization circuit according to this embodiment includes a synchronization signal detection circuit 1, an AND circuit 2, an OR circuit 3, a channel bit counter 4, a window generation circuit 5, an interpolation number count processing circuit. 21 and the OR circuit 7 are provided.
[0035]
The synchronization signal detection circuit 1 is configured to detect the synchronization signal from digital data that is reproduced from, for example, a CD and includes the synchronization signal for each frame, and output the detected synchronization signal to the AND circuit 2. The AND circuit 2 is configured to extract the normal synchronization signal DTSYNC from the synchronization signal SYNC detected by the synchronization signal detection circuit 1 when the window signal from the OR circuit 7 is at the “H” level.
[0036]
The OR circuit 3 is configured to perform a logical OR operation on the synchronization signal DTSYNC from the AND circuit 2 and the synchronization signal IPSYNC for interpolation from the channel bit counter 4 and output the synchronization signal DTIPSYNC.
[0037]
The channel bit counter 4 performs a counting operation based on the synchronization signal DTIPSYNC from the OR circuit 3, outputs the count value (count value) to the window generation circuit 5, and at the time when the count value reaches a predetermined value. The interpolation signal IPSYNC for interpolation is output to the OR circuit 3.
[0038]
The window generation circuit 5 is configured to generate a window signal WIN0 based on the count value from the channel bit counter 4 and output it to the interpolation number count processing circuit 21 and the OR circuit 7, respectively.
[0039]
As illustrated in FIG. 2, the interpolation number count processing circuit 21 includes an interpolation number counter 211, a signal generation circuit 212, and a counter control circuit 213.
[0040]
As shown in FIG. 3G, the interpolation number counter 211 detects that the synchronization signal SYNC is not detected by the synchronization signal detection circuit 1 while the window signal WIN0 from the window generation circuit 5 is at “H” level. When the synchronization signal DTSYNC is not extracted from the AND circuit 2, the number of times is counted (see FIG. 3H).
[0041]
The signal generation circuit 212 has a window signal WIN1 that becomes “H” level as shown in FIG. 3I during a period when the count value from the interpolation number counter 211 is a predetermined value (“2” in this example). Is generated and output. Further, the counter control circuit 213 subtracts “1” from the count value of the counter 211 at a required timing based on the synchronization signal DTSYNC from the AND circuit 2 and the window signal WIN1 from the signal generation circuit 212 as described later. The subtracting signal to be generated and the initialization signal for initializing the counter 211 are generated.
[0042]
Here, the synchronizing signal detecting means corresponds to the synchronizing signal detecting circuit 1 in FIG. 1, the synchronizing signal extracting means is the AND circuit 2 and the window generating circuit 5 in FIG. 1, and the synchronizing signal interpolating means is the channel bit counter in FIG. 4, etc., the counting means corresponds to the interpolation number counter 211 in FIG. 2, and the control means corresponds to the interpolation number count processing circuit 21 in FIG.
[0043]
Next, the operation of the detection protection circuit of the synchronous circuit according to the embodiment having such a configuration will be described with reference to the time charts of FIGS. Here, FIGS. 4A to 4C show details of the operation in each part of FIGS. 3A to 3C.
[0044]
Now, at time t1 shown in FIG. 3, when the synchronization signal detection circuit 1 detects the synchronization signal SYNC as shown in FIG. 3B, the window signal from the OR circuit 7 at this time is as shown in FIG. 3C. “H” level. For this reason, the synchronization signal SYNC is extracted as a normal synchronization signal DTSYNC by the AND circuit 2 and then extracted as the synchronization signal DTIPSYNC by the OR circuit 3 and supplied to the channel bit counter 4.
[0045]
The channel bit counter 4 performs a counting operation based on the synchronization signal DTIPSYNC from the OR circuit 3, outputs the count value (count value) to the window generation circuit 5, and at the time when the count value reaches a predetermined value. The synchronization signal IPSYNC for interpolation as shown in FIG. 3 (E) is output to the OR circuit 3. The window generation circuit 5 generates a window signal WIN0 as shown in FIG. 3 (G) based on the count value from the channel bit counter 4, and outputs the window signal WIN0 from the interpolation number counter 211 of the interpolation number count processing circuit 21, and Each is output to the OR circuit 7.
[0046]
If the synchronization signal detection circuit 1 does not detect the synchronization signal SYNC at time t2, the AND circuit 2 does not output the normal synchronization signal DTSYNC. However, since the channel bit counter 4 outputs the synchronization signal IPSYNC for interpolation as shown in FIG. 3 (E) and is input to the OR circuit 3, the OR circuit 3 receives the synchronization signal IPSYNC. An interpolated synchronization signal DTIPSYNC is output (see FIG. 3F). At this time, since the normal synchronization signal DTSYNC was not obtained from the AND circuit 2, the fact is counted by the interpolation number counter 211, and the counted value is “1” as shown in FIG. Become.
[0047]
When the synchronization signal detection circuit 1 cannot detect the synchronization signal SYNC again at time t3, the OR circuit 3 outputs the synchronization signal DTIPSYNC interpolated by interpolation of the synchronization signal IPSYNC from the channel bit counter 4 Is done. At this time, the count value of the interpolation number counter 21 is “2” as shown in FIG. During the period when the count value is “2”, the window signal WIN1 generated by the signal generation circuit 212 is at the “H” level as shown in FIG. As shown in FIG. 3 (C), it becomes “H” level. The number of consecutive undetected times is 2 in this example, but any number is possible.
[0048]
Here, a more specific waveform of each part before and after time t3 is as shown in A of FIG. As can be seen, the channel bit counter 4 performs a counting operation at the rising edge of the clock PLCK (a signal generated from the PLL circuit 9 in FIG. 5), and outputs the synchronization signal IPSYNC when the counted value becomes “587”. Initialized at the falling edge of the synchronizing signal DTIPSYNC from the OR circuit 3. Further, the window signal WIN 0 output from the window generation circuit 5 becomes “H” level before and after “587” of the count value from the channel bit counter 4. In this example, it is ± 4PLCK.
[0049]
When the synchronization signal detection circuit 1 detects the synchronization signal SYNC at time t4, the window signal output from the OR circuit 7 at this time is at the “H” level, so that the synchronization signal SYNC is Extracted as signal DTSYNC. At this time, the counter control circuit 213 generates a subtraction signal based on the falling edge of the synchronization signal DTSYNC from the AND circuit 2 and the falling edge of the window signal WIN1 from the signal generation circuit 212. The data is sent to the insertion number counter 211 (see the portion B in FIG. 4). As a result, the count value of the interpolation number counter 211 becomes “1” as shown in part B of FIG.
[0050]
At time t4, the window signal WIN1 output from the signal generation circuit 212 changes from the “H” level to the “L” level as shown in FIG. 3 (I), and is output from the OR circuit 7 accordingly. The window signal also changes from “H” level to “L” level as shown in FIG.
[0051]
When the synchronization signal detection circuit 1 cannot detect the synchronization signal SYNC at time t5, the operation of each unit is the same as that at time t3.
[0052]
When the synchronization signal detection circuit 1 detects the synchronization signal SYNC at time t6, the synchronization signal SYNC is extracted by the AND circuit 2 as a normal synchronization signal DTSYNC. At this time, since the counter control circuit 213 generates a subtraction signal and sends this subtraction signal to the interpolation number counter 211, the count value of the interpolation number counter 211 is “1”. At time t6, the window signal WIN1 output from the signal generation circuit 212 changes from the “H” level to the “L” level, and accordingly, the window signal output from the OR circuit 7 also changes from the “H” level to the “L” level. It changes to “L” level.
[0053]
Next, when the synchronization signal detection circuit 1 detects the synchronization signal SYNC at time t7, the synchronization signal SYNC is extracted by the AND circuit 2 as a normal synchronization signal DTSYNC. At this time, as shown in FIG. 3C, the counter control circuit 213 generates an initialization signal based on the synchronization signal DTSYNC from the AND circuit 2 and the window signal WIN1 from the signal generation circuit 212. Is sent to the interpolation number counter 211. As a result, the count value of the interpolation number counter 211 is initialized to “0” as shown in FIGS. 3 (H) and 4 (H).
[0054]
The signal waveform SIG shown in FIG. 4F is generated based on the synchronization signal DTSYNC from the AND circuit 2 and the window signal WIN0 from the window generation circuit 5, and the synchronization signal DTSYNC is at the “H” level of the window signal WIN0. It is a signal which shows that it detected in the period.
[0055]
As described above, in the synchronization signal detection protection circuit according to this embodiment, the synchronization signal SYNC is not detected at time t6 after the synchronization signal detection circuit 1 cannot continuously detect the synchronization signal SYNC at times t2 and t3. If it is detected, the synchronization signal is once estimated as a normal one. Thereafter, when the synchronization signal SYNC is detected again at time t7 after the elapse of a predetermined period from time t6, the synchronization signal at time t6 is detected. Was fixed as a regular one.
[0056]
On the other hand, the synchronization signal SYNC is detected at time t4, but since the synchronization signal SYNC could not be detected at time t5 after the elapse of a predetermined period from time t4, the synchronization signal at time t4 is determined to be normal. It does n’t come.
[0057]
Therefore, in the synchronization signal detection protection circuit according to this embodiment, while ensuring the reliability of resynchronization, the time until the resynchronization takes place is advanced by one synchronization signal compared to the conventional circuit of FIG. Therefore, the resynchronization time can be shortened.
[0058]
Further, in the synchronization signal detection protection circuit according to this embodiment, only the interpolation number counter 6 of the conventional circuit of FIG. 5 is replaced with the interpolation number count processing circuit 21, and the configuration of the other parts is the same as that of the conventional circuit of FIG. Since they are the same, the circuit scale can be reduced as compared with the conventional circuit of FIG.
[0059]
In this embodiment, the digital data including the synchronization signal is reproduced from the CD. However, in the present invention, as long as the digital data includes the synchronization signal every predetermined cycle, the digital data such as a DVD is used. The present invention can also be applied to digital data reproduced from various recording media.
[0060]
【The invention's effect】
As described above, according to the present invention, when the synchronization signal is not detected continuously for a predetermined number of times, the synchronization signal detected thereafter is estimated and extracted as a normal synchronization signal, After that, when the synchronization signal is detected again after the lapse of a predetermined period, the synchronization signal is extracted, and the previously detected synchronization signal is determined as the normal synchronization signal. In addition, the time until resynchronization can be shortened while ensuring the performance, and the circuit scale can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
2 is a block diagram showing a detailed configuration of an interpolation number count processing circuit shown in FIG. 1; FIG.
FIG. 3 is a time chart for explaining the operation of the embodiment of the present invention.
4 is a time chart in which the main part of FIG. 3 is enlarged.
FIG. 5 is a block diagram showing a configuration of a conventional circuit.
6 is a time chart for explaining the operation of the circuit of FIG. 5;
FIG. 7 is a block diagram showing another configuration of a conventional circuit.
8 is a time chart for explaining the operation of the circuit of FIG. 7;
[Explanation of symbols]
1 Sync signal detection circuit
2 AND circuit
3, 7 OR circuit
4 channel bit counter
5 Window generation circuit
21. Interpolation count processing circuit
211 Interpolation counter
212 Signal generation circuit
213 Counter control circuit

Claims (2)

Synchronization signal detection means for detecting the synchronization signal from digital data including a synchronization signal for each frame, synchronization signal extraction means for extracting the detected synchronization signal based on its periodicity, and the synchronization signal detection means A synchronization signal interpolation means for interpolating the synchronization signal when the synchronization signal is lost without being detected; and a counting means for determining the number of times the synchronization signal detection means cannot be detected when the synchronization signal detection means cannot detect the synchronization signal. In the sync signal detection protection circuit,
When the count value of the counting means reaches a first predetermined value, the synchronization signal extracting means makes it possible to extract the synchronization signal. If a synchronization signal is detected in this state, the synchronization signal is normalized. The synchronization signal is extracted by the synchronization signal extraction means and the count value of the counting means is set to a second predetermined value.
When the synchronization signal is detected without the count value of the counting means reaching the first predetermined value, the synchronization signal is extracted, and the previously detected synchronization signal is determined as a normal synchronization signal, A synchronization signal detection protection circuit comprising control means for controlling the count value of the counting means to be initialized.   2. The synchronization signal detection protection circuit according to claim 1, wherein the second predetermined value set by the counting means is a value obtained by subtracting 1 from a count value immediately before the set.

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