JPH07109981B2 - Sync signal detection circuit - Google Patents

Description

The present invention relates to a sync signal detection method for detecting a sync signal of a sampled format optical disc or the like.

[Outline of Invention]

In the present invention, in order to detect the sync signal by comparing the interval between the two edge pulses of the input signal with the reference interval, the middle of the two edge pulses is masked when the sync signal is stably detected.

[Background technology]

In a sampled format optical disc, a servo byte of a first byte and a second byte is arranged in each servo field, and each byte is composed of 15 ch bits. Furthermore, 3ch bit or 4ch of the first byte
A tracking pit is pre-arranged in either one of the bits and the 8ch bit. A segment synchronization signal (hereinafter, simply referred to as “synchronization signal”) is arranged in advance in the 8th bit of the first byte and the 12th bit of the second byte, and the interval of the synchronization signal is 19ch clock. Here, the channel clock is a clock that modulates 8-bit data into 15-ch bit data and corresponds to the modulated data. Since the data is less than 18ch clock, 19ch
Pits at clock intervals are detected as synchronization signals.

FIG. 3 is a block diagram of a conventional synchronizing signal detecting device.
The RF signal (Fig. 4 (a)) reproduced and output from the optical disc (not shown) is differentiated to generate an edge pulse (Fig. 4 (b)) corresponding to the prepit. This edge pulse is input to the counter 1. When the edge pulse is loaded, the counter 1 resets the count value so far and then starts counting the input clock. In the window decoder 2, the count value of the counter 1 is
The section window pulse is output from when it reaches 18 (= 19-1) to when it exceeds 20 (= 19 + 1). When an edge pulse of 12ch is input 19 clocks after an edge pulse of 8ch is input, the AND gate 3 is rendered conductive, and a sync signal detection signal is output.

When the interval between the two edge pulses is shorter than the 19ch clock, the counter 1 is reloaded when the second edge pulse is input and the count value is reset. When the interval is longer than 19ch clock, the window decoder 2 outputs an overflow signal and the counting operation of the counter 1 is prohibited. Then, the counter 1 is reloaded when the next edge pulse is input. When the interval is different from the sync signal, the sync signal detection signal is not output.

[Problems to be solved by the invention]

Since the conventional device detects the synchronization signal as described above, noises, defects, etc. are present between the two edge pulses constituting the synchronization signal, as shown in FIGS. 4 (c) and 4 (d), for example. When a pulse caused by the above is generated, there is a drawback that the sync signal cannot be detected.

Therefore, the present invention enables a sync signal to be correctly detected even if there is such a defect.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an interval between two edge pulse signals corresponding to two prepits when reproducing an information storage medium having two prepits for segment synchronization in a servo field. Is a predetermined reference interval, whether or not the normal sync signal is detected at least twice continuously in a predetermined cycle in the sync signal detection circuit that detects the two edge pulse signals as the normal sync signal. If it is determined that a normal synchronizing signal is detected at least twice in succession in a predetermined cycle based on the determination signal and a determination means that determines whether or not the determination signal is generated, two pulse signals are output. Signal generation means for generating a mask signal for masking between the two, and two edge pulse signals are extracted by masking the reproduction signal with the mask signal. Comprising a signal extraction means that, the.

[Action]

According to the present invention, the discriminating means discriminates whether or not the normal synchronizing signal is detected at least continuously twice or more in a predetermined cycle, and generates the discriminating signal. The signal generating means masks a signal between the two pulse signals when it is determined based on the determination signal that a normal synchronization signal is detected twice or more at least continuously in a predetermined cycle. To generate. The signal extracting means extracts the two edge pulse signals by masking the reproduction signal with the mask signal.

As a result, the signal extracting means masks the reproduced signal with the mask signal even if noise occurs between the two edge pulse signals, so that the synchronizing signal included in the reproduced signal can be accurately detected.

〔Example〕

FIG. 1 is a block diagram of a synchronizing signal detecting apparatus of the present invention, and the portions corresponding to those in FIG. 3 are designated by the same reference numerals.

At the time of initialization such as immediately after the driving of the device is started, the synchronization signal is not yet stably detected. At this time, the synchronization completion signal (FSOK) output by the protection circuit 12 is a logic L.
Becomes Therefore, the logic H symbol is input to the AND gate 11 via the inverter 14 and the OR gate 15. As a result, the edge pulse input to the AND gate 11 is directly supplied to the counter 1, the counter 1 and the window decoder 2
The synchronizing signal is detected by the circuit composed of the AND gate 3 as in the case described above.

The detection signal output from the AND gate 3 is supplied to the protection circuit 12. The protection circuit 12 is, for example, as shown in FIG. 2, a first circuit 31 including a counter 21, a window decoder 22 and an AND gate 23, a counter 24 and a window decoder.
A second circuit 32 including 25 and an AND gate 26, an RS flip-flop 27 and an AND gate 28. The circuits 31 and 32 are the counters 1 and 2 of FIGS.
It basically has the same configuration as the circuit including the window decoder 2 and the AND gate 3. However, the window decoders 22 and 25 are set with a reference interval of 270 ± 1 ch clock which is an interval of servo bytes.

When the detection signal of the synchronizing signal is input from the AND gate 3, the counter 21 starts counting the clock. In the window decoder 22, the count value of the counter 21 is 269, 270 or
At 271, a logic H signal is output as a window.
As a result, the AND gate 23 outputs a signal of logic H when the interval between two consecutive detection signals is 270 ch clock. That is, the circuit 31 detects the interval of the synchronization signal.

When the output of the AND gate 23 is input, the counter 24 starts counting clocks. The window decoder 25 outputs a logic H when the count value of the counter 24 is 269, 270 or 271. Therefore, the AND gate 26 outputs a signal of logic H when the interval between the outputs of two consecutive AND gates is 270 ch clock. That is, by the circuit 32,
It is determined whether or not the sync signal with the correct interval has been detected twice in succession.

When a signal of logic H is input from the AND circuit 26, the RS flip-flop 27, which has been reset by the reset pulse at the time of initialization, is set and outputs the synchronization completion signal (FSOK) of logic H. When the flip-flop 27 is set, the AND gate 28 becomes conductive, and the synchronization signal detection signal from the AND gate 3 is output to the decoder 13 as it is. When the detection signal is input from the AND gate 28, the decoder 13 outputs a window pulse of a predetermined width at the timing of the 8ch edge pulse and the 12ch edge pulse of the next servo byte with reference to the position (position of the synchronization signal). To do. When the flip-flop 27 is set, the output of the inverter 14 becomes logic L, so that the output of the decoder 13 is supplied to the AND gate 11 via the OR gate 15. Therefore, after that, AND gate 11 outputs 8ch edge pulse and 12c
Only the h edge pulse is passed and the other edge pulses are masked.

It is possible to mask the middle part (mirror part) of the two edge pulses that make up the sync signal even at the time of initialization, but doing so will cause the data signal to be erroneously detected as the sync signal and be detected correctly. Since it takes time, it is preferable not to mask at this time.

〔effect〕

As described above, according to the present invention, the signal extraction means masks the reproduction signal with the mask signal when the synchronization signal at the correct interval is detected at least twice. As a result, it is possible to accurately detect the sync signal included in the reproduction signal, which prevents data from being erroneously detected as the sync signal, and an edge pulse is generated due to a defect in the disk in the middle of the reference interval. Even then, stable detection of the synchronization signal becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronizing signal detecting device of the present invention, and FIG.
FIG. 4 is a block diagram of the protection circuit, FIG. 3 is a block diagram of a conventional synchronizing signal detecting device, and FIG. 4 is its timing chart. 1 …… Counter 2 …… Window decoder 3 …… And gate 11 …… And gate 12 …… Protection circuit 13 …… Decoder 14 …… Inverter 15 …… Or gate 21 …… Counter 22 …… Window decoder 23 …… And gate 24 …… Counter 25 …… Window decoder 26 …… And gate 27 …… RS flip-flop 28 …… And gate 31,32 …… Circuit

Claims (1)

[Claims] 1. When reproducing an information storage medium having two prepits for segment synchronization in a servo field, an interval between two edge pulse signals corresponding to the two prepits is a predetermined reference interval. At this time, in a sync signal detection circuit that detects the two edge pulse signals as a normal sync signal, it is determined whether or not the normal sync signal is detected at least twice continuously in a predetermined cycle. A discriminating means for generating a discriminating signal, and between the two pulse signals when it is discriminated based on the discriminating signal that the normal synchronizing signal is detected twice or more at least continuously in a predetermined cycle. Signal generating means for generating a mask signal for masking, and the two edge pulses by masking the reproduction signal with the mask signal. Synchronization signal detection circuit, characterized in that it and a signal extraction means for extracting items.