JP3210323B2 - RESYNC detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RESYNC detection circuit for detecting a synchronization code pattern called RESYNC inserted into a reproduced signal in an information recording device or an information transmission device. .

In this specification, an optical disk drive device will be described as an example for explanation, but the present invention is not limited to an optical disk, but a magnetic disk or a disk using another recording medium.
Alternatively, it can be used for an information reproducing apparatus such as a tape or a card, or a receiving unit of an information transmitting apparatus.

2. Description of the Related Art FIG. 11A shows an example of a sector format of a write-once or rewritable optical disk. RESYNC is a byte in the data section at regular intervals, for example,
For 20 bytes or 15 bytes, a plurality of RESYNCs are inserted such as one byte. When the data modulation method is the (2,7) code recording method, the RESYNC pattern is (2,7), for example, “0010 0000 0010 0100”.
It is unlikely to appear in the data pattern according to the coding rule. Therefore, a pattern with a low possibility of erroneous detection is selected. DATA, CONTROL, EC
A more detailed example of the format of the C, CRC and RESYNC parts is shown in FIG. 11B. As shown in FIG. 11B, normally, SYNC and subsequent RESYNC are inserted at regular intervals. In the figure, SB is SYNC
RS is RESYNC.

RESYNC is detected by a pattern matching circuit comprising a shift register 121 and AND gates 122 to 124 as shown in FIG. In the circuit of FIG. 12, when the pattern of "100000001001" is input to the shift register,
The detection signal becomes “1”. The RESYNC pattern usually selects a pattern that does not appear in the DATA pattern.However, a window is set to prevent erroneous detection of RESYNC due to deterioration in the quality of the playback signal, and a window is detected within that window.
In many cases, only the RESYNC detection signal is recognized.

FIG. 13 is a block diagram of a conventional RESYNC detection circuit, and FIG. 14 is a time chart showing the operation of the circuit of FIG. No.
The third pulse in FIG. 14 is a result of erroneously detecting RESYNC, but prevents the pulse from being output erroneously due to the window. The window generation circuit 13 in FIG.
3 counts clocks based on the SYNC signal from the SYNC detection circuit 132, and outputs the RESYNC pattern matching circuit 131
Is a circuit that generates a window that opens near the region where the RESYNC detection signal output from the above is estimated to be generated. This window must not be too wide or too narrow. The clocks shown in FIGS. 12 and 13 are generated by a PLL circuit and used in synchronization with the reproduced signal.

FIG. 15 is a circuit block diagram of a general information reproducing apparatus. In brief, the operation is as follows. Data recorded on the recording medium 150 is detected as an analog signal by the detector 151 and binarized by the binarization circuit 152. The sector mark detector 153 detects a sector mark (SM in FIG. 11A) from the binarized signal, and the read gate generator 154 opens the gate of the read data. PLL circuit is data synchronizer 155
, The data synchronizer 155 includes the synchronized clock 155a and the synchronized data synchronized with the clock.
Outputs 155b. The clock 155a and the synchronization data 155b are composed of a decoder 156 for outputting decoded data, an address mark (AM in FIG. 11A) detector 157 for detecting an address mark, and
It is input to a SYNC / RESYNC detector 159 which detects SYNC and RESYNC. The output of the address mark detector 157 is input to the lead clock generator of the preformat unit,
A clock that leads the preformat part shown in FIG. On the other hand, the output signal from the SYNC / RESYNC detector 159 is input to the lead clock generator 160 in the data section,
A clock for reading the data portion shown in FIG. 11A is generated. The output of FIG. 15 is output in the form of decoded data and a lead clock synchronized therewith, as in the time chart of FIG.

Here, the function of RESYNC is that when the clock generated by the PLL is out of phase or the number of periods is out of order due to the lack of a reproduced signal or the deterioration of signal quality, etc.
This is for reconfirming the position of the data. Therefore, if the detection window of the RESYNC is too narrow, when the clock from the PLL is disturbed, the RESYNC protrudes from the window, thereby making it impossible to read after that position. On the other hand, if the window is too wide, a spurious RESYNC pattern caused by an error in the data is erroneously detected, so that reading cannot be performed thereafter.

[Problems to be Solved by the Invention] By the way, the reproduction signal quality is degraded by factors such as aging of media and components of the apparatus, media quality factors, reproduction environment factors, and the like. Therefore, if the quality of the reproduced signal is degraded, the recorded data signal disappears or becomes garbled, causing various problems.

The present invention provides a RESYNC detection circuit that maintains high quality information reproduction by solving the following problems.

I want to be able to read correctly by detecting RESYNC even when SYNC cannot be detected correctly due to deterioration of the reproduction signal quality. Because this type of information recording device has an error code correcting function usually called ECC, even if one block from SYNC to the first RESYNC cannot be reproduced completely, If the data can be correctly reproduced, the data in that sector can be correctly restored.

The RESYNC window is preferably set based on the previous RESYNC or SYNC. Otherwise, if you set it based on the first SYNC or sector mark,
It becomes impossible to respond flexibly to clock phase shift and frequency shift due to signal quality deterioration in the data section.

In order to satisfy the requirements, the RESYNC window must be expanded as much as possible. And the window is SYNC
Must not be smaller than the window. If the RESYNC window is narrower than the SYNC window under the conditions, the signal quality deteriorates near the SYNC pattern and the fake SY
If an NC pattern is generated and the SYNC error detection position is located on the outermost side of the wide window, the next RESY
Even if the NC can be played back correctly, the RESYNC window will be too narrow and the RESYNC will protrude from the window.
Detection becomes impossible, and the sector cannot be reproduced.

Conversely, the RESYNC window must not be too wide. Normally, the SYNC window is set with reference to the time point of the last data of the sector mark or the preformat portion. Therefore, the SYNC window needs to have a certain width in order to cope with the fluctuation of the physical reproduction speed. Also, since the RESYNC pattern is usually shorter, for example, SYNC is 3 bytes and RESYNC is 1 byte, it is impossible to make the RESYNC window wider than the SYNC window. In other words, if the RESYNC pattern is short but the RESYNC window is too wide, the risk of erroneously detecting the RESYNC pattern due to signal quality deterioration is undesirably increased.

I want to be able to correctly reproduce data even when the RESYNC pattern disappears due to reproduction quality deterioration. For this purpose, even when a RESYNC pattern is not detected in the window, an operation is performed as if the RESYNC pattern correctly existed at the position where the RESYNC pattern is assumed to have disappeared, estimated from the previous RESYNC pattern. It is most preferred to do so.

To do so, the RESYNC window must be symmetrical about the correct RESYNC position. If not, when false detection of RESYNC due to signal quality deterioration,
Even if the next RESYNC is played back correctly, there is a possibility that it will be out of the window. Also, all RESYNC windows must be of a fixed length. If this is not the case, there is a possibility that the next correct RESYNC will fall out of the window when the RESYNC is detected.

If two RESYNCs are erroneously detected in the window due to signal quality deterioration, at least one of them is a fake RESYNC. In this case, it is necessary to output only one RESYNC detection pulse. If it is not so, and if one should output two or more RESYNC detection pulses, the fifteenth
Even if the number of read clocks in the data section in FIG. 16 and FIG. 16 does not match, and RESYNC or data is correctly reproduced at a later time, a data bit shift occurs as in the case of a wrong button, and the sector is reproduced. Because they can no longer do it.

[Means for Solving the Problems] In order to solve this problem, a RESYNC detection circuit of the present invention comprises: an estimation pulse setting means for setting a normal RESYNC estimation pulse after a predetermined time from a previous SYNC or a RESYNC detection pulse;
Window setting means for providing a window of a predetermined width before and after the estimation pulse; RESYNC detection means for detecting RESYNC in the window; and RESYNC detection when only two or more RESYNC detection pulses are detected in the window. Output as a detection pulse, and when only one RESYNC detection pulse is detected, output as it is as a RESYNC detection pulse,
When the RESYNC detection pulse is not detected,
A pulse output unit that outputs a RESYNC estimation pulse as a RESYNC detection pulse; anda delay unit that delays the SYNC detection pulse, the RESYNC detection pulse, and the normal RESYNC estimation pulse by an equal time, wherein the RESYNC detection pulse or the normal RESYNC estimation pulse is It is output at a time later than the window.

Here, the window is symmetric with respect to the normal RESYNC estimation pulse before and after. If the window is SYNC
It has the same length as the detection window. Also, the RESY
The logical sum of the NC detection pulse or the normal RESYNC estimation pulse and the SYNC detection pulse is calculated and output as a SYNC or RESYNC pulse.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a first configuration example of the SYNC / RESYNC detector of the present embodiment. An embodiment of the window circuit 12 in FIG. 1 is shown in FIG. 4A, and its time chart is shown in FIG.
Shown in the figure.

Window open signal 3a and window close signal
5a is a pulse signal for indicating the start point and end point of the RESYNC window. The window is symmetrical with respect to the normal RESYNC estimation pulse by setting the day 5 in FIG. 1 one clock longer than the day 4. That is, in Fig. 4B, the regular RESYNC
The first and second window lengths of the pulse are equal.

As shown in FIG. 4A, the matching signal 11a is supplied to the AND gate 45.
Window open signal 3a and window close signal
The gate is gated in a window 41a between 5a and only the matching signal 11a in the window is output as a RESYNC detection pulse 12a. However, when one matching signal 11a appears in the window, the signal 46c is fed back to close the window through the OR gate 44,
The second matching signal 11a appearing in the window is ignored.

In FIG. 4B, A is a regular RESYNC pattern detection pulse, B
This is the second pulse in the window generated by the RESEARCH. Then, this circuit recognizes and outputs only the first pulse A in the window and ignores the second B as shown in FIG. 4B. Also ignore the fake RESYNC "C" that is off the window.

FIG. 2 is a circuit diagram showing a first embodiment of the delay circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a second embodiment. The long delay is a circuit composed of the counters 21 to 23, the flip flops 24 to 27 and the inverter 28 shown in FIG.
Short delays are more efficient with the circuit comprising flip-flops 31-3n of FIG.

In FIG. 1, first, a SYNC detection signal 15a is generated from a reproduced signal by a SYNC detection circuit 15. Next, several daylays 2, 3, 4
The first RESYNC position is estimated by the function of
A RESYNC estimation pulse is generated, and a pulse of a window open 3A and a window close 5a are generated before and after the RESYNC so that a window can be set to be symmetric about the estimated pulse between the delays 4 and 5. On the other hand, RESY
The matching signal 11a generated by the NC pattern matching circuit 11 is used by the window circuit 12 so that no more than two pulses are output within the window, and is used as a RESYNC detection pulse.
12a.

The pulse presence / absence determination circuit 13 comprises a flip-flop 51 and an inverter 52, as shown in FIG. 5, and outputs "1" when one or more pulses exist in the window, and "0" when no pulse exists. Output. The selector circuit 14 outputs a RESYNC detection pulse when the determination signal is “1”, and a normal pulse when the determination signal is “0”.
The RESYNC estimation pulse is selected and output.

However, the completion of the pulse presence / absence determination must be after the window, so the selector
A delay 1b having a length equal to or longer than the latter half of the window must be provided at the entrance of the selector 14 so that the normal RESYNC estimation pulse is not input to the selector 14. In addition, the RESYNC pulse is also adjusted to the same length as day 1b.
1c is provided. As a result, the final RESYNC signal is always output with a certain delay, but this can be solved by delaying the output of the decoder by the same length. Referring to FIG. 15, a delay having the same length as the delay 1b may be provided before or after the decoder 156. In addition,
Whenever the circuit shown in FIG. 4 is used as the window circuit 12 in this embodiment when the delay 1c is equal to the delay 1b, since the output of the window circuit already has one clock delay for the input, the delay 1c It is correct to make the length of 1 clock shorter than day 1b. Likewise
The SYNC detection signal from the SYNC detection circuit 15 is also delayed by the delay 1a similarly to the delay 1c. As described above, the length of the delay is slightly different depending on the implementation circuit, but is not related to the essence of the present invention.

When the RESYNC is detected in the reproduced signal by the operation of the above circuit, the selector 14 in FIG.
When RESYNC cannot be detected from the NC detection signal due to deterioration of the reproduction signal quality, a normal RESYNC estimation pulse is output instead. The selector output 14a is supplied to the S circuit by the OR circuit 16.
It is output as one signal together with the YNC signal. Further, the RESYNC pulse is input to the delay 2 again, and the RESYNC pulse becomes a reference point of the next RESYNC pulse, and the next RESYNC position is estimated.

The above operation is continued until the read gate signal 154a in FIG. 15 becomes inactive.

By these operations, the normal RESYNC estimation pulse estimated from the previous SYNC or RESYNC detection pulse is set,
In addition, a window is provided at the same length before and after the estimated pulse, so that one RESYNC is output within the window. When RESYNC is not detected, the normal RESYNC estimated pulse is output instead of the RESYNC detection pulse. Become so.

FIG. 6 is a time chart for explaining the operation when both SYNC and RESYNC are normal. Thus, RESYNC detected after the window is closed is output as an output signal.

FIG. 7 shows a time chart for explaining the operation when the RESYNC disappears. When the RESYNC pattern disappears due to the deterioration of the reproduction signal quality, the pulses of the matching signal disappear as shown in FIG. In this figure, SYNC is detected correctly and the first
RESYNC was also correctly detected, indicating that the second RESYNC has disappeared. Even in this case, the select circuit 14
By selecting the SYNC estimation pulse, the RESYNC signal is output, and the data can be correctly reproduced. Also, the next RESYNC detection window is set at the correct position.

FIG. 8 is a time chart showing the operation when the fake RESYNC pattern occurs. This figure shows that although SYNC was correctly detected and the first RESYNC was also correctly detected, an error occurred in the reproduced signal and the spurious RE was detected in the second RESYNC detection window.
This shows a case where a SYNC pattern has appeared but no abnormality has occurred in the third RESYNC.

In this case, the appearance of the RESYNC pattern in the second RESYNC portion causes the output SYNC / RESYNC signal to output an erroneous pulse before the correct position,
Further, although the window position of the third RESYNC detection is erroneously shifted forward, the third RESYNC signal is output due to the correct detection of the third RESYNC, and the fourth RESYNC signal is output.
The RESYNC detection window is also set correctly. In the information reproducing apparatus of this embodiment, even if a situation as shown in this figure occurs, the second RESYNC portion, that is, 20 bytes or 15 bytes of the third data block cannot be reproduced, but after the next block. Can be correctly reproduced, and the error-reproduced code can correctly reproduce the unreproducible sector.

FIG. 9 is a time chart showing the operation when the false SYNC pattern occurs. This figure shows a case where a large abnormal signal is generated in the SYNC pattern portion and the SYNC pattern is erroneously detected at an incorrect position, but RESYNC is correctly detected. As shown in the figure, even if the false SYNC is erroneously detected just before the correct position, if the amount of deviation is within the width of the RESYNC window, the first RESYNC detection window deviates, but the RESYNC is correctly detected. Also, the second
The RESYNC detection window after RESYNC is set correctly. When the situation as shown in this figure occurs, the information reproducing apparatus of the present embodiment cannot reproduce 20 bytes or 15 bytes of the first data block, but can reproduce correctly after the second block. The sector of the first data block can be correctly reproduced by the function of the code.

Furthermore, if the length of the RESYNC detection window is made equal to the length of the SYNC detection window, even if the SYNC pattern is lost due to the deterioration of the reproduction signal quality, the RESYNC
If data is correctly detected, the subsequent data can be reproduced, so that the sector of the first data block can be reproduced correctly.

It should be noted that, from Daylay 1a to Daylay 5, any configuration can be changed without changing the essence of the invention. For example, a change as shown in FIG. 9 can be easily made. In this figure, the day 6 is the length obtained by adding the day 4 and the day 5 shown in FIG. 1, and the day 7 is the length obtained by adding the day 4 and the day 1b. In this circuit, the normal RESYNC estimation pulse does not actually exist, but operates exactly the same as in FIG.

The normal RESYNC pulse and window described in this specification are set to be visible for ease of explanation. Even if the normal RESYNC estimated pulse and window are real signals as shown in FIG. Even if it does n’t exist in
Circuits having the same functions as the present invention are included in the present invention. Further, in addition to FIG. 10, any number of circuits having the same purpose and the same function can be considered by changing the combination of the delays and changing the shape of the signal, all of which are included in the present invention. For example, a method of generating and processing an actual window signal instead of the window open and window close pulse signals of the present invention is also conceivable.

According to the present invention, a normal RESYNC estimation pulse estimated from the previous SYNC or RESYNC detection pulse position is generated, a window is provided before and after the estimated pulse position, and RESYNC is detected in the window. If more than one RESYNC is detected, only one is output. If only one RESYNC is detected, it is output as it is. If no RESYNC is detected, the normal RESYNC estimation is performed. By providing a circuit that outputs a pulse as a RESYNC detection pulse and always outputs one optimal RESYNC detection pulse within a window, if the reproduction signal quality deteriorates, the SYNC pattern disappears. Even if the next RESYNC is played correctly, it can be played back, and even if the RESYNC pattern disappears, even the block where the RESYNC disappears will be correct. It can be reproduced.

Further, according to the present invention, the RESYNC window is
By having a symmetrical length and a constant length with respect to the SYNC pulse, even if a false RESYNC pattern is generated in the RESYNC window due to deterioration of the reproduction signal quality and is erroneously detected, the error is detected. Even if one block of the detected RESYN cannot be reproduced, if the next RESYNC can be reproduced correctly, it can be reproduced correctly from that point.

According to the present invention, the RESYNC window has the same length as the SYNC detection window.
Even if a pattern occurs and it is erroneously detected, if the next RESYNC can be reproduced correctly, it can be reproduced correctly from that point.

According to the present invention, the above-described RESYNC detection pulse and the normal RE
Delay the SYNC estimation pulse by the same length and RESYNC
By outputting the detection pulse at a time after the RESYNC window, the following is possible.

Further, according to the present invention, there is provided a RESYNC pulse presence / absence determination circuit for determining whether or not one or more RESYNC detection pulses have occurred in the RESYNC window, and the RESYNC detection pulse is delayed according to the determination result. By providing a circuit that selects one of the signal that has been subjected to the normal RESYNC position estimation pulse and the signal that has been delayed, and outputs the selected signal as the RESYNC signal, this can be realized.

According to the present invention, the SYNC detection signal is delayed by a length equal to the length obtained by delaying the RESYNC detection pulse and the normal RESYNC estimation pulse, and the logical sum of the RESYNC signal and the SYNC signal is calculated to obtain the SYNC and RESYNC signals. By providing a circuit that outputs at a time later than the SYNC window or the RESYNC window, it is possible to achieve the following.

[Effects of the Invention] According to the present invention, it is possible to provide a RESYNC detection circuit that maintains high quality of information reproduction. That is, when a RESYNC pattern cannot be detected and a RESYNC detection pulse is generated in a pseudo manner (in this case, since the determination of the presence or absence of the RESYNC detection pulse must be completed after the window, the pseudo RESY
Even when the NC detection pulse is generated after the window, the output timing of the SYNC detection pulse and the output timing of the RESYNC detection pulse can be matched to prevent a clock phase shift and a frequency shift.

More specifically, even when SYNC cannot be detected correctly due to the deterioration of the reproduction signal quality, it becomes possible to read correctly by detecting RESYNC.

Even if the RESYNC pattern is lost due to the deterioration of the reproduction signal quality, all data can be correctly reproduced.

Even if a fake RESYNC pattern appears due to remarkable deterioration of the reproduction signal quality, one block cannot be reproduced,
Subsequent blocks can be correctly reproduced. If the error correction code function is used together, the sector can be read without any problem.

Since the RESYNC detection window can be set wider and the ability to correct the RESYNC pattern can be sufficiently exhibited, the error occurrence rate of the entire apparatus is reduced.

For the reasons described above, the signal quality becomes stronger against deterioration, and the following effects are further obtained.

_{In the -1} recording generation device, the risk of being unable to be reproduced due to aging, environmental change, dirt, scratches, and the like of the medium can be reduced.

_{-2 In a} recording / reproducing apparatus, the risk that reproduction cannot be performed when a medium is moved to another drive apparatus due to a problem of compatibility of another drive apparatus can be reduced.

_{-3 In the} recording / reproducing device, the drive device can withstand signal quality deterioration, so that the quality use of the medium can be reduced by that much, so that the yield in media production can be improved, Manufacturing costs can be reduced.

_-4 recording and reproducing apparatus, according to the present invention, RESYNC
Since the error correction capability can be increased, a format having a long interval of the RESYNC pattern can be adopted, and the substantial recording density is improved by that amount.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first configuration example of the SYNC / RESYNC detector of the present embodiment, FIG. 2 is a circuit diagram showing a first embodiment of the delay circuit in FIG. 1, and FIG. 4A is a circuit diagram showing a second embodiment of the delay circuit in FIG. 1, FIG. 4A is a circuit diagram showing an embodiment of the window circuit in FIG. 1, and FIG. 4B is an operation of the window circuit in FIG. 4A. FIG. 5 is a circuit diagram showing an embodiment of the pulse presence / absence determination circuit in FIG. 1, FIG. 6 is a time chart for explaining an operation when a normal signal is input, and FIG. Is a time chart for explaining the operation when the RESYNC disappearance signal is input, FIG. 8 is a time chart for explaining the operation when the fake RESYNC pattern is input, and FIG. 9 is for explaining the operation when the fake SYNC pattern is input. FIG. 10 shows another configuration of the SYNC / RESYNC detector of this embodiment. FIG. 11A is a diagram showing an example of a sector format of an optical disk, FIG. 11B is a diagram showing an example of a format of a data section in FIG. 11, and FIG. 12 is a general RESYNC pattern. FIG. 13 is a circuit block diagram showing an example of a conventional RESYNC circuit, and FIG. 14 is a time chart showing the operation of the circuit of FIG. 13. FIG. 15 is a block diagram showing the configuration of a reproduced signal processing circuit in a general information reproducing apparatus, and FIG. 16 is a time chart for explaining the timing of the output signal of the circuit shown in FIG. In the figure, 1a to 1c, 2 to 7 ... delay circuit, 11 ... RESYNC pattern matching circuit, 12 ... window circuit, 13 ...
Pulse presence / absence determination circuit, 14 ... selector circuit, 15 ... SYNC
Detection circuit, 16: OR circuit, 17: D flip-flop,
151 Detector, 152 Binarization circuit, 153 Sector mark detector, 154 Read gate generator, 155 Data synchronizer, 156 Duplexer, 157 Address mark detector 158, a SYNC / RESYNC detector; 158, a preformat lead clock generator; 160, a data lead clock generator.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/10-20/14 H04L ^7/ 00-7/10

Claims (4)

(57) [Claims] 1. An estimation pulse setting means for setting a normal RESYNC estimation pulse after a predetermined time from a previous SYNC or RESYNC detection pulse; a window setting means for providing a window of a predetermined width before and after the estimation pulse; A RESYNC detection means for detecting the following: when two or more RESYNC detection pulses are detected in the window, only one is output as a RESYNC detection pulse;
When only one RESYNC detection pulse is detected,
Output as a RESYNC detection pulse, and when no RESYNC detection pulse is detected, the normal RESYNC estimation pulse
Pulse output means for outputting as a SYNC detection pulse, the SYNC detection pulse, the RESYNC detection pulse, and the normal RESYNC
A RESYNC detection circuit comprising: delay means for delaying an estimation pulse by an equal time, wherein the RESYNC detection pulse or the normal RESYNC estimation pulse is output at a time later than the window. 2. The method according to claim 1, wherein the window is symmetrical about the normal RESYNC estimation pulse.
RESYNC detection circuit according to 1. 3. The apparatus according to claim 1, wherein said window has a length equal to a window for detecting SYNC.
RESYNC detection circuit. 4. The logical sum of the RESYNC detection pulse or the normal RESYNC estimation pulse and the SYNC detection pulse is calculated, and the logical sum is calculated as SY
The RESYNC detection circuit according to claim 1, wherein the circuit outputs the signal as an NC or RESYNC pulse.