JPH04132431A - Resync detection circuit - Google Patents

Abstract

PURPOSE:To ensure an output of a proper RESYNC by outputting a position estimate pulse with priority when 2>= RESYNC signals are detected in a window and any of them is located at a position the same as that of the position estimate pulse. CONSTITUTION:The detection circuit is provided with a RESYNC pattern matching circuit 1, a window circuit 2, delay circuits 3-9, a pulse presence discrimination circuit 11, a normal RESYNC pulse presence discrimination circuit 12, a SYNC detection circuit 13, a selector 14, an OR gate circuit 15, a D flip- flop 16 and an AND gate circuit 17. In this case, when 2>= RESYNC signals in a window are detected and any of them is at the same position as the position estimate pulse, the pulse is outputted with priority. Thus, even when a false RESYNC pattern appears, the RESYNC is correctly detected and the correct operation is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a RESYNC detection circuit that detects a synchronization code pattern called RESYNC inserted into a reproduced signal in an information recording device or an information transmission device.

[Prior Art] FIG. 14 is a schematic diagram showing an example of a sector format of a write-once or rewritable optical disc.

Note that although an optical disk drive device will be explained here as an example, not only optical disks but also disks using magnetic disks and other recording media, and not only disks but also information reproducing devices such as tapes and cards, or information recording devices In addition, the present invention can be similarly applied to a receiving section of an information transmission device.

A plurality of RESYNCs are inserted into the data at regular intervals, one byte at a time, for example, one byte of RESYNC for 20 or 15 bytes of data.

Also, if the (2,7) code recording method is used, RESYNC
For example, the pattern is “001000000010010
According to the (2,7) code rule, a pattern such as ``0'' that is less likely to appear on a data pattern and therefore less likely to result in false detection is selected.

In addition, FIG. 15 shows rData in FIG. 14 above,
central, ECC, CRC and resin
In Figure 0, which is a schematic diagram showing a more detailed format example of the part ``c''ty), S R ka SY N Ct L,
R5 indicates RESYNC.

Typically a SYNC followed by a RESYN as shown.
C is inserted at equal intervals.

RESYNC is normally detected by a pattern matching circuit as shown in FIG.

This pattern matching circuit has a shift register 81 and gate circuits 82 to 84, and has a "100000001"
At the time when the pattern "001" has been input to the shift register 81, the detection signal output of the AND gate circuit 84 becomes "L".

The RESYNC pattern is usually selected from a pattern that does not appear in the data pattern, but in order to prevent erroneous detection of RESYNC due to deterioration in the quality of the reproduced signal, a predetermined window is set and the RESYNC detected within that window is selected. In many cases, only the detection signal is recognized.

FIG. 17 is a block diagram showing the RESYNC detection circuit, and FIG. 18 is a time chart showing the operation of the circuit.

This RESYNC detection circuit includes the pattern matching circuit 91 and the SYNC detection circuit 92.

It has a window generation circuit 93 and an AND gate circuit 94. The window generation circuit 93 is a circuit that counts clocks based on the SYNC signal and generates a window that opens near the area where the RESYNC detection signal is estimated to occur. It is.

The third pulse in FIG. 18 is a result of erroneously detecting RESYNC, but the window prevents the output of this erroneously detected pulse. Therefore, this window should neither be wide nor narrow.

The detailed reason for this will be explained below using an information reproducing device as an example.

FIG. 19 is a block diagram showing the configuration of the information reproducing device.

This device includes a detector 112 that detects a reproduced signal from a recording medium itt, a binarization circuit 113 that binarizes this detection signal, and a sector mark detector 114 that detects sector marks in the reproduced signal. A read gate generation circuit 115 that generates a read gate based on this sector mark, a data synchronizer circuit 116 (described later), a decoding circuit 117 for a reproduced signal, an address mark detector 118 that detects an address mark, and a read gate in the preformat section. A circuit 119 that generates a clock, a RESYNC detection circuit 120, and a circuit 1 that generates a read clock for the data section.
21.

In such a circuit, a clock synchronized with the reproduced signal is generated and used by a PLL circuit.

This PLL circuit is provided within the data synchronizer circuit 116. Data synchronizer circuit 116
outputs a synchronized clock and synchronized data synchronized by that clock.

The output of such an information reproducing apparatus is in the form of decoded data and a read clock synchronized with the decoded data, as shown in the time chart shown in FIG.

Now, returning to the RESYNC detection circuit 120, the RESYNC detection circuit 120 outputs the RESYNC detection circuit 120.
NC is used in the above information reproducing device to reconfirm the position of data when the phase of the clock generated by the PLL circuit shifts or the number of cycles shifts due to missing reproduced signals or deterioration of signal quality. be done.

Therefore, if the detection window of RESYNC is too narrow, when the PLL clock is disturbed, RESYNC will protrude from the window, making it impossible to read from that position onwards. Conversely, if the window is too wide, the data False RE caused by the above error
The S Y N C pattern is erroneously detected, and further reading becomes impossible.

[ff1iil to be solved by the invention Therefore, the present inventor took the above conditions into consideration and developed a suitable RESYNC
We have proposed a RESYNC detection circuit that can secure the output.

In other words, this RESYNC detection circuit detects the previous SYN
A window is provided before and after the normal RESYNC position estimation pulse position estimated from the C or RESYNC detection pulse position, and RESYNC is detected within that window.
If two ESYNCs are detected early, only one is recognized and output, and if only one RESYNC is detected, it is output as is and then RESYNC is detected.
If no C is detected, the above regular RES
The YNC position estimation pulse is output instead of the RESYNC detection pulse, so that one R
It outputs an ESYNC pulse.

However, for example, the quality of the reproduced signal in the above-mentioned device deteriorates due to factors such as aging, media quality, and reproduction environment. When the quality of the reproduced signal deteriorates, the data signal that should have been recorded may disappear. This can cause various problems if the data is lost or transformed into other data.

For example, the RES in the above-mentioned (2, 7) code recording method
YNC pattern is “0010000000100100
” is used. Also, assume that the 1-byte data immediately before RESYNC is “33hex”.

Then, the second example of the signal pattern recorded at this time is
Shown in Figure 1.

Here, when an extra pulse is generated due to deterioration in the quality of the reproduced signal, the bit that should originally be "O" becomes 1" in the bit string reproduced by the generation of the extra pulse, and then The location is 21st
If it occurs at the position shown in the figure, as shown in Figure 21, the false (7) RESYNC pattern will appear before the true RESYNC pattern.
SYNC pattern appears, then RESY
29 NC detection pulses will be generated. In this case, it is desired to give priority to the second biased true pulse.

By the way, the regular RESYNC position estimation pulse is a pulse set by counting the clock based on the previous SYNC or RESYNC position, and is a pulse set by counting the clock based on the previous SYNC or RESYNC position.
If the C detection pulse is correct, it indicates the correct RESYNC detection pulse position unless a clock synchronization shift occurs on the way.

And the RESYNC detection window is the regular RESYNC detection window.
The window is set around the NC position estimation pulse, and if this window is kept narrow, the false R
ESYNC can be ignored. However, as mentioned earlier, if the window is narrowed, the correct RESYNC
It is conceivable that they may be taken away. Furthermore, R.E.
RESY even if the SYNC pattern cannot be detected.
If you want to enable playback by detecting NC, the RESYNC window needs to be the same size as the SYNC window, and in the example of Figure 21, ±
A space of about 16 clocks is required. However, if the window is made to have a width of ±16 square meters, as shown in Figure 21, the fake RESYN-C pattern will also be incorporated, and the real RESYNC pattern will be displayed within one window.
A plurality of detection pulses including the detection pulse will be generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a RESYNC detection circuit that can select and output an appropriate RESYNC when a plurality of detection pulses are generated within a window.

[Means for Solving the Problems 1] The present invention sets a regular RESYNC position estimation pulse estimated from the existing SYNC or RESYNC detection pulse position, provides a window before and after this estimated pulse position, and performs RESYNC within that window. is 2
If more than one value is detected, only one is recognized and output, and if only one RESYNC is detected, it is output as is, and if no RESYNC is detected. In this case, the estimated pulse RESY
A RESYNC detection circuit that outputs instead of NC,
Two or more RESYNCs are detected within the window,
Moreover, if any of them is located at the same position as the position estimation pulse, that pulse is output with priority.

[Operation] In the present invention, two or more RESYNCs are detected within a window, and one of them is a regular RESYNC.
If the pulse is located at the same position as the SYNC position estimation pulse, that pulse is output with priority to ensure proper RESYN.
You can select and output C.

[Example] FIG. 1 is a schematic diagram showing an embodiment of the present invention.

This RESYNC detection circuit includes a RESYNC pattern matching circuit 1, a window circuit 2, delay circuits 3 to 9, a pulse presence/absence determination circuit 11, and a normal RESYNC detection circuit.
C pulse presence/absence determination circuit 12, SYNC detection circuit 13, selector 14, OR gate circuit 15, and D free 2
It has a flip-flop 16 and an AND gate circuit 17.

FIG. 2 is a circuit diagram showing a specific example of each delay circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing another specific example of each delay circuit.

It is efficient to use the circuit shown in FIG. 2 for long delays, and the circuit shown in FIG. 3 for short delays.

4 is a circuit diagram showing the configuration of the window circuit in FIG. 1, and FIG. 5 is a time chart showing the operation of the window circuit.

The window oven signal and window close signal are
This is a pulse signal for indicating the start and end points of the RESYNC window.

By setting the delay circuit 9 of the RESYNC detection circuit one clock longer than the delay circuit 8, the pulse becomes symmetrical with respect to the regular REsYNc position estimation pulse. In other words, as explained in Fig. 5, the regular RESY
The lengths of the first and second half windows are equal for the NC estimated pulse.

In Figure 5, A is the regular RESYNC pattern detection pulse, B is the 2 pulses generated within the window by the false RESYNC.
This is the second pulse.

The window circuit 2 recognizes and outputs pulses A and B located within the window, and ignores and does not output pulses C located outside the window.

Figure 6 shows a normal SYNC, R signal in the RESYNC detection circuit.
5 is a time chart showing an operation when an ESYNC signal is input.

The RESYNC detection circuit first detects the SYNC from the playback signal.
The detection circuit 13 generates a SYNC detection signal.The first RESYNC position is estimated by @3 of the 0-order delay circuits 3 to 9, and a regular RESYNC position estimation pulse is generated. Generate window open and window close pulses to set a window that is symmetrical about .

On the other hand, the matching signal generated by the RESYNC pattern matching circuit 1 is recognized by the window circuit 2, delayed by the delay circuit 5, and unified into one pulse so that two or more pulses are not output.

FIG. 7 is a circuit diagram showing an example of the delay circuit 5.

When a plurality of RESYNC detection pulses are inputted to the delay circuit 5, only the first pulse among them is delayed and output.

FIG. 8 is a circuit diagram showing the pulse presence/absence determination circuit 11.

This pulse presence/absence determination circuit 11 outputs "1" when one or more pulses exist within the window, and outputs "0" when no pulse exists.

FIG. 9 is a circuit diagram showing the normal RESYNC pulse presence/absence determination circuit 12.

The normal RESYNC pulse presence/absence determining circuit 12 determines whether or not a matching signal pulse exists at the same position as the normal RESYNC position estimation pulse. If present, consider it a normal RESYNC pulse;
Outputs “L”.

Furthermore, if it does not exist, H'' is output.

AND gate circuit 17 connects the pulse presence/absence determination signal and the normal R
An AND with the ESYNC pulse "absence" signal is determined and inputted as a select signal to the selector 14.

As a result, the selector 14 outputs a single RESYNC detection pulse output from the delay circuit 5 only when one or more RESYNCs are detected within the window and their detected positions differ from the estimated pulse positions. Select.

On the other hand, if RESYNC is not detected within the window, or if RESYNC is detected and there is a pulse that matches the estimated pulse position, the selector 14 selects the normal R
Select ESYNC position estimation pulse.

However, the determination of the presence or absence of a pulse must be completed after the window, so selector 1 must be
In order to prevent the regular RESYNC position estimation pulse from being input to the selector 14, a delay circuit 4 with a length equal to or longer than the second half of the window must be provided at the entrance of the selector 14. A delay circuit 5 having the same length as the circuit 4 is provided.

As a result, the final RESYNC signal is always output for a certain period of time, but this can be solved by delaying the output of the decoder 117 shown in FIG. 11 by the same length. . That is, before or after the decoder 117.

It is sufficient to provide a delay circuit with a length equal to that of the delay circuit 4. Note that even if the delay circuit 5 and the delay circuit 4 are made equal, the window circuit 2 is
When using the configuration shown in FIG. 4, the output of the window circuit 2 already has a delay of one clock with respect to the input, so the length of the delay circuit 5 is
It is correct to make the delay length l clocks shorter than the delay length.As described above, the length of the delay differs slightly depending on the implementation circuit, but it is not related to the essence of the present invention.

Next, the selector signal is converted to S by the OR gate circuit 15.
Together with the YNC signal, this signal is output as one signal.

Further, the RESYNC pulse is re-inputted to the delay circuit 6, and the RESYNC pulse is input to the next RESYNC pulse.
This becomes the reference time point for the YNC pulse, and the next RESYNC position is estimated.

The above operation continues until the read gate signal becomes inactive.

By the above operation, the previous SYNC or RESYNC
A normal RESYNC position estimation pulse estimated from the detected pulse position is set, and a window of equal length is provided before and after the estimated RESYNC position, and within that window, R
Ensure that less than one ESYNC is output, and RESYN
When C is not detected, a regular RESYNC position estimation pulse is output instead of a RESYNC detection pulse.

FIG. 1O is a time chart showing the operation of the RESYNC detection circuit when the RESYNC disappearance signal is input.

When the RESYNC pattern disappears due to quality deterioration of the reproduced signal, the pulse of the matching signal disappears as shown in Figure 10. In this figure, SYNC was detected correctly and the first RESYNC was also detected correctly, but the second This shows a case where the second RESYNC disappears. Even in this case, the selector 14 selects the regular RESYNC position estimation pulse, so that a correct RESYNC signal is output and data can be correctly reproduced. Furthermore, the next RESYNC detection window is also set at the correct position.

FIG. 11 is a time chart showing the operation when a false RESYNC pattern occurs.

This figure shows that SYNC is correctly detected and the first RESY
NC was also detected correctly, but an abnormality occurred in the reproduction signal and a false RESYNC was detected within the second RESYNC detection window.
A case is shown in which there is no abnormality in the third RESYNC even though the C pattern has appeared.

In this case, the second RESYNC part contains a false RESYNC.
Due to the appearance of the C pattern, the output RESYN
The C signal outputs an erroneous pulse before the correct position, and the window position for 3rd RESYNC detection has shifted forward by mistake.
is correctly detected, the third RESYNC detection signal is also correctly output, and furthermore, the window for fourth RESYNC detection is also set correctly.

In the information reproducing device, when the situation shown in Fig. 11 occurs, the second RESYNC part, that is, 20 or 15 bytes of the 1g3 data block, cannot be reproduced, but the next block and subsequent blocks can be reproduced correctly. , the sector can be correctly reproduced by the action of the error correction code.

FIG. 12 is a time chart showing the operation when a false RESYNC pattern occurs.

This figure shows a case where a large abnormal signal occurs in the RESYNC pattern portion and the RESYNC pattern is erroneously detected at an incorrect position, but RESYNC is correctly detected.

As shown in the figure, even if a false RESYNC is erroneously detected before the correct position, as long as the amount of deviation is within the width of the RESYNC window, RESYNC will be correctly detected even though the first RESYNC detection window is shifted. . In addition, the RESYNC of the second RESYNC
The detection window is also set correctly. When a situation like the one shown in FIG. 12 occurs, the information reproducing device
Although 20 to 15 bytes of the first data block cannot be reproduced, the second and subsequent blocks can be reproduced correctly, so that sector can be correctly reproduced by the action of the error correction code.

Additionally, the length of the RESYNC detection window can be set to SYNC
If the length is set equal to the length of the detection window, even if the SYNC pattern is lost due to quality deterioration of the reproduced signal, if RESYNC is detected correctly, subsequent data can be reproduced, so that sector can be reproduced correctly. I can do it.

Next, the operation when the pattern shown in FIG. 21 mentioned above is input will be explained.

As mentioned above, the pattern in Fig. 21 generates a false RESYNC pattern near the true RESYNC pattern due to the generation of the extra pulse, thereby creating two RESYNC detection pulses, one genuine and one false. Occur.

FIG. 13 is a time chart showing the operation in this case.

In Figure 13, SYNC and the first RESYNC were detected correctly, but in the second RESYNC, the pattern shown in Figure 21 occurred, resulting in two RESYNC detection pulses, one real and one fake. It shows.

At this time, the normal RESYNC pulse presence/absence determination circuit 12 in FIG. 1 outputs "L" since there is a normal pulse. Therefore, the output of the AND gate circuit 17 becomes "L", and the selector 14 outputs the output of the delay circuit 8 (regular RES).
YNC position estimation pulse). Then, in this case as well, a correct RESYNC signal is output.

Therefore, in this case as well, due to the generation of extra pulse,
Despite the appearance of a false RESYNC pattern, data can be reproduced without error.

As described above, in this example, due to the deterioration of the reproduced signal,
False RESYNC near regular RESYNC pattern
Even if a pattern appears, the data can be correctly reproduced. Therefore, the RESYNC detection window can be set wider, and even if SYNC cannot be detected correctly,
Data can be correctly reproduced by detecting RESYNC.

Further, for the above reasons, the following effects occur in the recording/reproducing apparatus.

(1) It is possible to reduce the risk of the recording medium becoming unplayable due to aging, environmental changes, dirt, scratches, etc.

(2) Due to compatibility issues between the recording medium and the drive device,
It is possible to reduce the risk that the medium cannot be played back if it is moved to another drive device.

(3) Since the drive device can be made resistant to signal quality deterioration, the quality specifications of the medium can be lowered by that amount, which improves the yield of media production and reduces the cost of manufacturing the media. I can do it.

(4) Since the error correction ability of RESYNC can be improved, a format with a long interval between RESYNC patterns can be adopted, and the actual recording density can be improved accordingly.

In addition, in the above embodiment, the SYNC and RESYNC detection circuit of the optical disk drive device was explained.
This can be applied to any circuit, regardless of whether it is a recording device or a communication device, as long as it detects a synchronization pattern with a constant period.

Furthermore, SYNC and RESYNC may be the same pattern; in detecting the same pattern at a constant period, the synchronization pattern detected first can be regarded as the synchronization pattern detected after the 12th SYNC. In that sense, the present invention can also be used to detect sector marks in, for example, optical disk drives. Alternatively, the present invention can also be used to extract clock pits from a sample servo type optical disc.

Furthermore, it is also possible to make various modifications to the circuit configuration shown in FIG. 1 without changing the gist of the present invention.

For example, various combinations of delays can be considered to set the necessary timing. Further, the pulse presence/absence determination circuit 11 and the normal RESYNC pulse presence/absence determination circuit 12 may be combined and replaced with another circuit having the same function. Furthermore, there is also a method of not using the selector 14 but instead using the reset function of the delay circuit 9 and the delay circuit 8.

[Effects of the Invention] As described above, according to the present invention, even if a false RESYNC pattern appears near a regular RESYNC pattern, RESYNC can be detected correctly and correct operation can be ensured. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a RESYNC detection circuit according to one embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific example of each delay circuit provided in the above embodiment. The third @ is a circuit diagram showing another specific example of each of the delay circuits described above. FIG. 4 is a circuit diagram showing the configuration of the window circuit provided in the above embodiment. FIG. 5 is a time chart showing the operation of the window circuit. FIG. 6 is a time chart showing the operation when normal SYNC and RESYNC signals are input to the RESYNC detection circuit of the above embodiment. FIG. 7 is a circuit diagram showing an example of the configuration of the delay circuit of the above embodiment. FIG. 8 is a circuit diagram showing a pulse presence/absence determination circuit provided in the above embodiment. FIG. 9 is a circuit diagram showing a normal RESYNC pulse presence/absence determination circuit provided in the above embodiment. FIG. 1O is a time chart showing the operation of the RESYNC detection circuit in the above embodiment when the RESYNC disappearance signal is input. FIG. 11 is a time chart showing the operation when a false RESYNC pattern occurs in the RESYNC detection circuit of the above embodiment. FIG. 12 is a time chart showing the operation when a false RESYNC pattern occurs in the RESYNC detection circuit of the above embodiment. FIG. 13 is a time chart showing the operation when two RESYNC detection pulses, one genuine and one false, are generated due to the generation of an extra pulse in the RESYNC detection circuit of the above embodiment. FIG. 14 is a schematic diagram showing an example of a sector format of a conventional write-once or rewritable optical disc. FIG. 15 is a schematic diagram showing a part of the format in FIG. 14 in more detail. FIG. 16 is a circuit diagram showing an example of a pattern matching circuit for detecting RESYNC. FIG. 17 shows R using the above pattern matching circuit.
FIG. 2 is a block diagram showing an example of an ESYNC detection circuit. FIG. 18 is a time chart showing the operation of the RESYNC detection circuit shown in FIG. 17. FIG. 19 is a block diagram showing the configuration of an information reproducing device for boat fishing. FIG. 20 is a time chart showing an output signal of the information reproducing device. FIG. 21 shows that the RESYNC detection circuit shown in FIG.
12 is a time chart showing an example of a signal pattern when four RESYNC detection pulses are generated. 1... RESYNC pattern matching circuit, 2...
・Window circuit. 3 to 9... Delay circuit, 11... Pulse presence/absence determination circuit, 12... Normal RESYNC pulse presence/absence determination circuit, 13
...SYNC detection circuit. 14...Selector, 15...OR gate circuit, 16...D flip flow, 17...AND gate circuit.

Claims (1)

[Claims] In addition to setting a regular RESYNC position estimation pulse estimated from the existing SYNC or RESYNC detection pulse position, a window is provided before and after this estimated pulse position, and within that window, RESYNC is binarized. If more than one RESYNC is detected, only one is recognized and output, and if only one RESYNC is detected, it is output as is, and if no RESYNC is detected, then , a RESYNC detection circuit that outputs the estimated pulse in place of RESYNC, and when two or more RESYNCs are detected within the window,
Moreover, if any of them is located at the same position as the position estimation pulse, the RESYNC detection circuit is characterized in that it outputs that pulse with priority.