JP2522832B2 - Demodulation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit for reproducing data including a digitally recorded resynchronization signal from a medium.

2. Description of the Related Art Optical recording discs are provided with optically detectable guide tracks such as guide grooves in a concentric circle shape or a spiral shape for reasons such as high density recording tracks, discrete partial writing, and erasing. The recording layer formed on this guide track is irradiated with laser light whose diameter is 1 μm or less,
Recording is performed by making holes or changing reflectance and transmittance.

When recording digital information having a variable data length, a track is divided into a plurality of sectors in order to increase recording efficiency, and information is recorded and reproduced in sector units. Each sector is composed of a sector ID part including track address and sector address information and a data field part for recording / reproducing data. The data to be recorded in this data field section is normally PLL (Phase Locked Loop)
A sync pull-in signal part for the sync pull-in, a data head identification mark DM (hereinafter referred to as a data mark) added before the recorded data to identify the head of the data, and a data part. , Word synchronization for demodulation is established by detecting a data mark in the reproduced signal.

On the other hand, when various defects, dust, scratches, etc. exist on the base material, recording film, protective layer, etc. of the optical recording disc, dropout is generated in the reproduction signal. Is as small as about 1 μm, the raw error rate is very poor at 10 ⁻⁵ to 10 ^−6, and there are many long burst-like dropouts.
This burst-shaped dropout is often a PL during playback.
A bit slip phenomenon occurs that affects the L operation and the oscillation frequency of the PLL changes, and the number of self-regenerated clocks increases and decreases, and word synchronization is lost during data demodulation, and all subsequent sector data is in error. May be.

In order to solve such a problem, a means for inserting a reproduction synchronizing signal into the sector data at a constant interval when recording is taken. An example of this format is shown in FIG. Sector data is provided for synchronization pull-in signal (SYNC) 1 for PLL synchronization pull-in, data mark (DM) 2 for identifying the beginning of data, and at regular intervals to re-synchronize data demodulation. Resync signal RESYNC (R
S) 3 and a data part 4 divided into m blocks (hereinafter referred to as a frame). Data recording / reproduction is performed by detecting the sector identifier (ID) 5 at the beginning of the sector and reading the address of the target sector. With this configuration, even if the demodulation word synchronization is deviated due to the bit slip phenomenon caused by the long dropout as described above, the error is suppressed by the resynchronization signal on a frame-by-frame basis. , Normal demodulation can be executed.

However, in the sector format with a frame structure, if the resync signal cannot be detected due to dropout when demodulating the data, the data of the frame is not stored in the sector buffer memory and resync is performed at the wrong position. If a signal is detected, incorrect data is stored in the sector buffer memory in that frame, and the resynchronization prediction signal goes to the wrong position as it is, so the data is stored in the buffer memory with the data shifted, and error correction becomes impossible. Sometimes.

However, even if the length of continuous demodulation error due to the bit slip phenomenon is limited by adopting the data format to which the resynchronization signal 3 is added as described above, bit slip occurs. In such a case, normal data also becomes a continuous burst error due to error propagation, so the error correction capability is significantly reduced, and if a resynchronization signal is not detected, it will be stored in the sector buffer memory in a misaligned manner. (Slip phenomenon), and sometimes it became uncorrectable.

The present invention solves such a problem, and in order to improve the correction capability for an error caused by a bit slip, demodulation is performed when the occurrence of the bit slip is detected during reproduction of data having a resynchronization signal addition format. By performing bit shift on the output data obtained by, or masking the reproduction signal when the re-synchronization signal is not detected, and forcibly storing the data corresponding to one frame in the sector buffer memory. It is an object of the present invention to provide a demodulation circuit that improves the error correction capability.

Means for Solving the Problems In order to solve the above problems, the present invention provides a demodulation circuit for reproducing data including a resynchronization signal recorded on a recording medium having a sector structure for each block. Means for detecting the resynchronization signal from the reproduced signal, demodulation means for detecting the resynchronization signal from the reproduced signal and demodulating the data, means for storing the demodulated data for each block in the sector buffer memory, Means for predicting the next resync signal detection position from the sync signal, means for comparing the detected resync signal position with the predicted resync signal position, and the detection state of the resync signal obtained by the comparison means And means for storing the resynchronization signal in each block, and bit-shifting the output data obtained from the demodulation means to re-demodulate the data. And a forced data storage means for forcibly storing data corresponding to one block in a predetermined position of the sector buffer memory when a block in which the re-synchronization signal cannot be detected is detected from the reproduction signal. Even if a frame slip phenomenon is detected by recognizing the detected state of the output data that has been output, forcibly storing one frame worth of data in the sector buffer memory and demodulating the data normally, this is due to a false detection of the playback sync signal. When a bit slip occurs and a data error occurs, retry the reproduction signal and determine where the bit slip occurred based on the detection status of the resynchronization signal, and use data masking means to mask the reproduction signal near the occurrence point. This is provided to prevent erroneous demodulation due to the resynchronization signal.

Operation With the above-described configuration, when the data is reproduced, by knowing the detection state of the resynchronization signal for each reproduced frame, it is possible to detect a bit slip caused by a long dropout existing on the disc, which is obtained by demodulation. The output data is bit-shifted, the reproduction signal is masked when the resynchronization signal is not detected, and the data corresponding to one frame is forcibly stored in the sector buffer memory. It is possible to reduce the error in and improve the error correction ability.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an information recording / reproducing apparatus according to an embodiment of the present invention. The reproduction signal 100 read from the optical disk 6 by the photodetector 7 and amplified by the preamplifier 8 is waveform-shaped by the waveform equalization circuit 9 and digitized by the comparator 10 to become the binarized reproduction signal 101. On the other hand, the address of the sector identifier portion ID is read by the address reproducing circuit 11,
The address reproduction signal 102 of the sector is output.

CPU12 that controls the data when demodulating data in a certain sector
Confirms the address reproduction signal 102 and outputs the demodulation command signal 103 for the target sector to the demodulation circuit 13. Demodulation circuit 13
Then, the PLL circuit 14 self-generates the reproduction clock 104 for the binarized reproduction signal 101, and executes the demodulation operation according to the reproduction clock 104. In the data mark detection circuit 15 and the resynchronization signal detection circuit 16, the input binarized reproduction signal 10
When the data mark and the bit pattern of the resynchronization signal appear in 1, the data mark detection signal 105 (hereinafter D
An M detection signal) and a resynchronization signal detection signal 106 (hereinafter referred to as an RS detection signal) are output. The demodulation timing gate signal generation circuit 17 creates a demodulation timing gate signal 107 in frame units according to these signals and inputs the demodulation timing gate signal 107 to the demodulation unit 18, and the demodulation unit 18 demodulates one sector. Demodulation unit
When the data mask gate circuit 28 is not used, the demodulated data A108 output from 18 is the demodulated data B1 through.
As 09 or while a part of the demodulated data A108 is masked by the information of the RS information generation circuit 26, the data mask gate circuit 28 converts it into dummy data, for example, all “0” data or all “1” data. Replace and demodulate data B1
As 09, it is sent to the RAM control circuit 19 together with the RAM write gate signal 110 output from the demodulation timing gate signal generation circuit 17, and written in the RAM 20. When the demodulated data of all the frames are written in the RAM 20 and the demodulation operation of one sector is completed, the error correction detection circuit 21 checks the error of the demodulated data by the error correction code added at the time of recording, and corrects any error. Generate correct data.

Next, the bit slip detection circuit will be described.
As described above, the bit slip is detected from the detected position of the pre-existing data mark DM or the resynchronization signal RS by using the PLL14
The reproduction clock 104 is counted for one frame to predict the position of the resynchronization signal RS of the next frame, and the position of the detection signal of the resynchronization signal RS is compared with the position of the prediction signal. This will be described with reference to FIG. 1. The RS detection signal 106 and the mask gate signal 111 for masking the false re-synchronization signal detection are logically ORed by the AND gate 22, and the output 112 thereof is input to the clear terminal of the counter 23. The counter 23 receives the reproduction clock 104 of the PLL 14 as a clock input and reproduces the reproduction clock for one frame.
Counting 104, RS prediction signal 1 by decoder 24
13 is output to the resynchronization position comparison circuit 25. In the position comparison circuit 25, the RS detection signal 106 is output within the window signal 114 having a width of ± several bits with respect to the output position of the RS detection signal 106.
The position of the RS prediction signal 113 is compared with the position of the RS prediction signal 113 to detect the presence or absence of bit slip, and the RS information generation circuit 26 generates the RS information 115 indicating the detection state of the resynchronization signal and the RAM control circuit
Sent to 19.

As the RS information 115, the following four types are generated depending on the positional relationship between the RS prediction signal 113 and the RS detection signal 106 in the set window signal 114.

(1) Normal detection: The RS detection signal 106 was obtained at the same position as the RS prediction signal 113.

(2) Advance detection ... The RS detection signal 106 was obtained at a position which is advanced in time with respect to the position of the RS prediction signal 113 (the number of clocks of the PLL 14 in one frame is reduced, and the RS prediction signal 113 is originally Was obtained later than the occurrence position of.

(3) Delay detection: The RS detection signal 106 was obtained at a position delayed in time with respect to the position of the RS prediction signal 113 (the number of clocks of the PLL 14 in one frame is increased, and the RS prediction signal 113 is originally Was obtained earlier than the occurrence position of).

(4) Undetected ... RS detection signal 106 in window signal 114
Alternatively, the RS prediction signal 113 was not obtained.

The RS information 115 is written in the demodulation data management area of the RAM 20 during demodulation, and is used when the error cannot be corrected even after error detection and correction, and the cause is bit slip. To do.

FIG. 2 is a diagram showing the timing of the window signal 114. FIG. 2A shows a binarized reproduction signal 101, and FIG. 2B shows RS.
Detection signal 106, (C) is window signal 1 for RS detection
14 is shown. The window signal 114 is generated by performing PLL clock count for one frame from the RS detection signal 106 detected in the previous frame. 2 (D), (E),
(F) and (G) are an enlarged view of the RS portion of the binarized reproduction signal 101, an enlarged view of the RS detection signal, a PLL clock, and an enlarged view of the window signal, respectively. As shown in FIG. 2 (D),
Assuming that the resynchronization signal RS is composed of m bits from RS1 to RSm, the RS detection signal 106 is the RS signal detection circuit 16
When the m-th bit of the RS pattern is input to, the RS signal is output from the RS signal detection circuit 16. A window signal 114 of several bits before and after the position of the RS detection signal 106 is generated, and the resynchronization position comparison circuit 25 compares the positions of the RS detection signal 106 and the RS prediction signal 113 in the window signal. This window width is determined by how long one frame is and how many clocks of the PLL 14 may increase or decrease in that length. At most, 1-2 bits are sufficient.

Next, the timing of the RS information generation circuit 26 of FIG. 1 will be described in detail. FIG. 3 is a detailed timing chart of the RS information generation circuit 26. As the RS information 115, (1) normal detection, (2) advance detection, (3) delay detection, (4) non-detection,
There are four types of output signals, which are the RS detection signal 106, the RS prediction signal 113, the window signal 114, and the PLL reproduction clock 104.
Is generated as input. The RS information 115 is generated for each RS section shown in the format of FIG.
It is assumed that the information is generated when the window signal 114 is closed as shown in FIG. 3, and that state is detected when each output is at a high level at that time. After the RS information 115 is transmitted in each frame, all the flip-flops are cleared by the reset signal, and the configuration returns to the initial state. Also, the RS information 115 is the R of the next frame.
Since it is generated in the S section, the bit slip occurrence state in the final frame cannot be compared with the RS predicted signal 113 in position because there is no reference RS. Therefore, when trying to detect the bit slip state in the last frame, it is necessary to add an extra RS to the end of the sector data.

When demodulation using this RS information 115 is executed, R
This demodulation method is not normally used because it takes time to read data from the AM or error register and bit shift processing, and if this demodulation is performed only when an error that cannot be corrected by an error occurs, the speed is normally reduced. It is possible to suppress the demodulation error in the sector in which the bit slip has occurred and improve the correction capability without dropping the value.

Next, the RS information 115 when the resynchronization signal is erroneously detected will be described with reference to FIG. When the resynchronization signal is normally detected, the RS information 115 is basically (1) normal detection. In case of false detection, (2) advance detection and (3)
There is also a case of delay detection, but in this case there is no problem.
(4) If it is judged that the clock has not been detected, there is a significant increase or decrease in the PLL14 clock, and the RS detection signal 106 and RS
The RS information is (4) undetected because the predicted resynchronization signal of the next block also appears in the wrong position unless the predicted signal 113 is present or the resynchronization signal is not erroneously detected again from the reproduction signal in the window signal 114. Then, the bit slip state continues unless any abnormal processing is performed thereafter. When the RS detection signal is continuously lost, (4) the undetected state continues, but the probability is low. Therefore, if a bit slip has occurred and error correction is not possible, and if the same sector is retried again, RS information 114
(4) When there are two or more undetected states in succession, M number of (4) undetected states before and after the first (4) undetected block are ( M ≧
2) When detected above, the reproduced signals from (N-1) block to N block are masked by using the data mask gate circuit 28, and the data corresponding to one frame is forcibly stored in the sector buffer memory. It suffices to perform demodulation according to. Even in the above case, if the error cannot be corrected, masking is performed in the Nth block and the (N + 1) th block, and the same retry process as described above may be performed thereafter. Alternatively, (4) the data of the block immediately preceding the undetected block may be masked, and the retry process may be performed thereafter in the same manner as above. As shown in the figure, the shorter the mask gate length, the higher the reliability of the demodulated data. It may be easier to control the mask gate externally by arbitrary or in block units.

Further, although an optical disc has been described as an example in the present embodiment, it goes without saying that a medium for recording / reproducing information in sector units such as a magnetic disc or a floppy disc does not impair the purpose.

As described above, according to the present invention, the resynchronization signal is set to 1
When demodulating data included in each block, it is possible to detect bit slips caused by long burst errors existing on the disk, and by storing the detection status of the resynchronization signal, the PLL clock may increase or decrease. Or you can prevent the frame slip phenomenon,
The obtained demodulated data has a great effect of reducing errors during demodulation.

[Brief description of drawings]

FIG. 1 is a demodulation block diagram in one embodiment of the present invention, FIG. 2 is a timing diagram of window signals, FIG. 3 is a timing diagram of RS information generation, and FIG. 4 is a timing diagram when a reproduced signal is masked. FIG. 5 is a sector format diagram including a resynchronization signal. 1 ... Sync pull-in signal (SYNC), 2 ... Data mark (DM), 3 ... Resync signal (RS), 5 ... Sector identifier (ID), 6 ... Optical disk, 7 ... Photodetector, 8: preamplifier, 9: waveform equalization circuit, 10: comparator,
11 ... Address reproduction circuit, 12 ... CPU, 13 ... Demodulation circuit, 14 ... PLL circuit, 15 ... Data mark detection circuit, 16
...... Resynchronization signal detection circuit, 17 ・ ・ ・ Demodulation timing gate signal generation circuit, 18 ・ ・ ・ Demodulation section, 19 ・ ・ ・ RAM control circuit, 20 ・ ・ ・ RAM, 21 ・ ・ ・ Error correction detection circuit, 23 ・ ・ ・ Counter, 24 ...... Decoder, 25 …… RS detection position comparison circuit,
26 ... RS information generation circuit, 28 ... data mask gate circuit, 100 ... reproduction signal, 101 ... binarized reproduction signal, 103 ...
... demodulation command signal, 104 ... reproduction clock, 105 ... DM detection signal, 106 ... RS detection signal, 107 ... demodulation timing gate signal, 108 ... demodulation data A, 109 ... demodulation data B,
110 …… RAM write gate signal, 111 …… Mask gate signal, 113 …… RS prediction signal, 114 …… Window signal, 11
5 ... RS information.

Claims (3)

(57) [Claims] 1. A demodulation circuit for reproducing data containing a resynchronization signal recorded on a recording medium having a sector structure for each block, a demodulation circuit for detecting the resynchronization signal from the reproduction signal, and a means for detecting the resynchronization signal from the reproduction signal. Demodulation means for detecting a sync signal to demodulate data, means for storing the demodulated data for each block in the sector buffer memory, and means for predicting the next resync signal detection position from the already detected resync signal And a means for comparing the detected resynchronization signal position with the predicted resynchronization signal position, and a means for storing the detection state of the resynchronization signal obtained by the comparison means. The state is the first state resynchronized at the same position as the resynchronization signal detection position where the resynchronization signal is expected to be detected, and the second state resynchronized at a position ahead of the expected resynchronization signal detection position. State of A third state resynchronized at a position delayed from the expected resynchronization signal detection position, a fourth state in which no resynchronization signal is detected at the expected resynchronization signal detection position, and a second state And in the third detection state, bit shift operation is performed on the output data obtained from the demodulation means to re-demodulate the data, and in the fourth detection state, data for masking the reproduction signal. A demodulation circuit having mask means and provided with a compulsory data storage means for compulsorily storing data corresponding to one block in a predetermined position of the sector buffer memory. 2. A demodulation circuit according to claim 1, wherein the masking timing of the reproduction signal data masking means is controlled arbitrarily from the outside. 3. The demodulation circuit according to claim 2, wherein the mask control of the reproduction signal data mask means is performed in block units.