JPH0346166A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To decrease error at the time of demodulation in obtained demodulated data by detecting bit slip to be generated by long burst error existing on a disk when the data, which includes re-synchronizing signals for each block. CONSTITUTION:Demodulated data 108 of all frames are written into a RAM 20 and when demodulating operation to one sector is completed, an error correcting and detecting circuit 21 checks the error of the demodulated data according to an error correcting signal which is added at the time of recording. When there is the error, it is corrected and proper data are generated. Next, the detection of the bit slip generated by the long burst error existing on the disk is executed by counting a reproducing clock 104 of a PLL 14 for one frame from the detecting position of a existing before hand data mark or a resynchronizing signal RS and comparing the position of the resynchronizing signal in the next frame with the position of a forecasting signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a demodulation circuit for reproducing digitally recorded data including a resynchronization signal from a medium.

Conventional technology Optical recording disks are provided with concentric or spiral guide tracks that can be optically detected, such as guide grooves, in order to increase the density of recording tracks, discrete partial writing, and erasing. The recording layer formed on the guide track is irradiated with laser light focused to a diameter of 1 μm or less to create holes or change the reflectance and transmittance to record.

When attempting to record digital information whose data length is variable, a track is divided into a plurality of sectors to increase recording efficiency, and information is recorded and reproduced sector by sector.

Each sector is composed of a sector ID section containing track address and sector address information, and a data field section for recording and reproducing data. The data recorded in this data field is normally PLL (Phase
It is composed of a synchronization pull-in signal section for synchronization pull-in of (Locked Loop), a data start identification mark DM (hereinafter referred to as data mark) that is added before the recorded data to identify the start of the data, and a data section, During data demodulation, word synchronization for demodulation is achieved by detecting data marks in the reproduced signal.

On the other hand, if there are various defects, dust, scratches, etc. on the base material, recording film, protective layer, etc. of the optical recording disk, dropouts will occur in the reproduced signal.

The recording bit and track pitch of an optical recording disk are 1
Because it is minute, on the order of μm, the raw error rate is to-'
It is very bad at ~10-6, and there are many long burst-like dropouts. This burst-like dropout often affects PLL operation during playback, changing the oscillation frequency of the PLL.

A bit slip phenomenon occurs in which the number of self-regenerated clocks increases or decreases, and word synchronization may shift during data demodulation, causing all subsequent sector data to become errors.

When recording to solve such problems.

Measures are taken to insert resynchronization signals into sector data at regular intervals. An example of this format is shown in FIG. 6. The sector data includes a synchronization pull-in signal (SYNC) 1 for PLL synchronization pull-in, a data mark (DM) 2 for identifying the beginning of data. It is provided at regular intervals and consists of a resynchronization signal RESYNC (R8) 3 for resynchronizing data demodulation, and a data section 4 divided into m blocks (hereinafter referred to as frames). Recording and reproduction of data is executed by detecting a sector identifier (ID) 5 at the beginning of the sector and reading the address of the target sector. With this configuration, even if demodulation word synchronization is lost due to a bit slip phenomenon caused by a long dropout as described above, the error will be suppressed in frame units by the resynchronization signal 3, and the error will be suppressed from the next frame. can perform normal demodulation.

However, in a sector format that has a frame structure, if a resynchronization signal cannot be detected due to dropout etc. when demodulating data, the data of that frame is not stored in the sector buffer memory, so subsequent frames may be shifted. The data will be stored in the memory as is, resulting in incorrect data.

Problems to be Solved by the Invention However, even if a data format with the above resynchronization signal 3 added is used to limit the length of continuous demodulation errors caused by the bit slip phenomenon, bit slips still occur. Due to error propagation, even normal data becomes continuous burst errors, resulting in a significant drop in error correction ability, and if a resynchronization signal is not detected, the data may be stored in the sector buffer memory with a shift (frame (slip phenomenon), resulting in a situation that cannot be corrected.

The present invention solves this problem, and in order to improve the ability to correct errors caused by bit slips, the present invention detects the occurrence of bit slips when reproducing data in a format with a resynchronization signal added, and detects the occurrence of bit slips and If the bit slip is not detected, the demodulation circuit is configured to forcibly store data equivalent to one frame in the sector buffer memory, thereby performing data recovery in the frame caused by the bit slip and improving the error correction ability. The purpose is to provide

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a demodulation circuit for reproducing data including a resynchronization signal for each block recorded on a recording medium having a sector structure. means for detecting a resynchronization signal from the resynchronization signal; demodulation means for detecting the resynchronization signal from the reproduced signal and demodulating the data; and means for storing data in a sector buffer memory for each block. means for predicting the next resynchronization signal detection position from the resynchronization signal; means for comparing the detected resynchronization signal position with the predicted resynchronization signal position; and detection of the resynchronization signal obtained by the comparison means. means for storing the state, and according to the detection state of the resynchronization signal in each block, performs a bit shift operation on the output data obtained from the demodulation means to demodulate the data again, and the resynchronization signal cannot be generated from the reproduced signal. forced data storage means for forcibly storing data equivalent to one block in a predetermined position of the sector buffer memory when a block is detected; The first state is resynchronized at the same position as the expected resynchronization signal detection position, the second state is resynchronized at a position further than the expected resynchronization signal detection position, and the expected resynchronization signal detection position is the same as the expected resynchronization signal detection position. The output obtained from the demodulating means has a third state in which the resynchronization is performed at a position delayed from the synchronization signal detection position and a fourth state in which the resynchronization signal is not detected at the expected resynchronization signal detection position. The system is configured so that the detected state of data is recognized and even in the case of a frame slip phenomenon, data corresponding to one frame is forcibly stored in the sector buffer memory so that the data can be demodulated normally.

With the above-described configuration, by knowing the detection state of the resynchronization signal for each reproduced frame during data playback, it is possible to detect bit slips caused by long dropouts on the disk, and to detect bit slips that occur when the resynchronization signal is not present. In the case of detection, data corresponding to one frame is forcibly stored in the sector buffer memory, data recovery is performed in frames, errors in the demodulation circuit can be reduced, and error correction capability can be increased.

Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an information recording and reproducing apparatus according to an embodiment of the present invention. A reproduced signal 100 read out from an optical disc 6 by a photodetector 7 and amplified by a preamplifier 8 is sent to a waveform equalization circuit 9. The signal is waveform-shaped and digitized by a comparator IO to become a binary reproduction signal 101. On the other hand, the address of the sector identifier part ID is read out by the address reproduction circuit 11, and the address reproduction signal 102 of the sector is output.

When demodulating data in a certain sector, CPU1 controls the
2 confirms the address reproduction signal 102 and outputs a demodulation command signal 103 for the target sector to the demodulation circuit 13. In the demodulation circuit 13, a PLL circuit 14 self-generates a reproduction clock 104 for the binary reproduction signal 101, and a demodulation operation is performed in accordance with this reproduction clock 104. In the data mark detection circuit 15 and the resynchronization signal detection circuit 16, when the bit patterns of the data mark, the data mark, and the resynchronization signal appear in the input binary reproduction signal 101, the data mark detection circuit 15 and the resynchronization signal detection circuit 16 each receive a data mark detection signal 105 (hereinafter referred to as A resynchronization signal detection signal 106 (hereinafter referred to as an RS detection signal) is output. The demodulation timing gate signal generation circuit 17 generates a demodulation timing gate signal 107 for each frame according to these signals and inputs it to the demodulation section 18, and the demodulation section 18 demodulates one sector. The output demodulated data 108 is sent to the RAM control circuit 1 along with the RAM write gate signal 109 output from the demodulation timing gate signal generation circuit 17.
9 and written into the RAM 20. The demodulated data 1o8 of all frames is written to the RAM 20,
When the demodulation operation for one sector is completed, the error correction detection circuit 2
In No. 1, errors in demodulated data are checked using an error correction code added during recording, and if any errors are found, they are corrected to generate correct data.

Next, a bit slip detection circuit will be explained. As mentioned above, bit slip detection is performed from the detection position of the data mark DM or resynchronization signal R5 that occurred the other night.
The position of the resynchronization signal R5 of the next frame is predicted by counting the reproduction clock 104 of L14 for one frame, and the position of the detected signal of the resynchronization signal RS and the predicted signal are compared.

To illustrate this with reference to FIG. 1, the R8 detection signal 106 and the mask gate signal 11 that masks false resynchronization signal detection
0 is logically summed by the AND gate 22 and its output 111
is input to the clear terminal of the counter 23. The clock counter 23 receives the reproduced clock 104 of the PLL 14 as an input, and when the reproduced clock 104 for one frame is counted, the decoder 24 outputs the R8 prediction signal 112.
is output to the resynchronization position comparison circuit 25. In this position comparison circuit 25, R8 is detected within the window signal 113 having the width of the overlay bit with respect to the output position of the R5 detection signal 106.
The positions of the detection signal 106 and the R8 prediction signal 112 are compared to detect whether a bit slip has occurred, and the R8 information generation circuit 26 generates R8 information 114 indicating the detection state of the resynchronization signal and sends it to the RAM control circuit 19. It will be done.

As the R8 information 114, the set window signal 1
R8 prediction signal 112 and R8 detection signal 10 in 13
The following four types are generated depending on the positional relationship of 6.

(1) The R5 detection signal 106 was obtained at the same position as the normal detection R8 prediction signal 112.

(2) R8 detection signal 106 relative to the position of advance detection RS prediction signal 112
was obtained at a temporally advanced position (P within one frame
The number of clocks of LL14 was reduced, and the R8 prediction signal 112 was obtained later than the original generation position).

(3) Delay detection R8 prediction signal digit 11112, R8 detection signal 10
6 was obtained at a temporally delayed position (the number of clocks of the PLL 14 within l frame increased, and the R8 prediction signal 112
was obtained earlier than the original location).

(4) The R8 detection signal 106 was not obtained within the undetected window signal 113.

This R8 information 114 is stored, for example, in the RAM 20 during demodulation.
It is written in the demodulated data management area of 1 and used when the error cannot be corrected even after error detection and correction, and the cause is bit slip occurrence.

FIG. 2 is a diagram showing the timing of the window signal 113. Figure 2 (A) is a binarized reproduced signal lot, (B)
shows the R8 detection signal 106, and (C) shows the window signal 113 for R8 detection. This window signal 113 is generated by counting the PLL clock for one frame from the R5 detection signal 106 detected in the previous frame. are doing. FIGS. 2(D), (E), (F), and (G) are enlarged views of the R8 portion of the binarized reproduced signal 101, and R8, respectively.
FIG. 6 is an enlarged view of a detection signal, a PLL clock, and a window signal. As shown in FIG. 2(D), if the resynchronization signal R5 is composed of m bits from the R8 part to the R8 part, the R8 detection signal 106 is sent to the R8 signal detection circuit 16 using the m bits of the RS pattern. The R8 signal is output from the R8 signal detection circuit 16 at the time when the eye is input. A window signal 113 of several bits before and after the position of this R8 detection signal 106 is generated, and the resynchronization position comparison circuit 25 compares the RS detection signal 106 and the RS prediction signal 1 within the window signal.
The window width for performing 12 position comparisons is determined based on the length of one frame and how many clocks the PLL 14 may increase or decrease in that length. However, 1 to 2 bits is usually sufficient.

Next, the timing of the R8 information generation circuit 26 shown in FIG. 1 will be explained in detail. FIG. 3 is a detailed timing diagram of the R3 information generation circuit 26. The R8 information 114 is (1
) Normal detection, (2) Advance detection, (3) Delay detection, (4)
There are four types: undetected and undetected, and this output signal is the R8 detection signal 106. R8 prediction signal 112, window signal 113,
It is generated using the recovered clock 104 of the PLL as input.

The RS information 114 is generated for each R8 part shown in the format of FIG.
As shown in the figure, this is done when the window signal 113 is closed, and when each output is at a high level at that time, it is assumed that this state has been detected. RS information 1 in each frame
]4, all flip-flops including the counter 23 are cleared by the reset signal.

Configure to return to initial state. Also, R8 information 114
is generated in the R8 portion of the next frame, so the bit slip occurrence state in the final frame is determined by the reference R8.
Since there is no R8 prediction signal 112, it is not possible to compare the position with the R8 prediction signal 112. Therefore, when trying to detect a bit slip state in the final frame, the R8 prediction signal 112 is not present at the end of the sector data.
It is necessary to add an extra 8.

Also, when demodulating using this R8 information, RA
Normally, this demodulation method is not used because it requires time to read data from the M or error register and perform bit shift processing, and if it is performed only when an uncorrectable error occurs, the speed will usually be reduced. It is possible to suppress demodulation errors in the sector where a bit slip has occurred and improve correction ability without compromising the performance.

FIG. 4 shows a timing chart when predicting the next resynchronization signal detection position from the resynchronization signal detected from the reproduced signal. FIG. 4A shows a normal case. first R8
After the detection signal 106 is detected, the counter 23 outputs the RS prediction signal 112 to the same position as the next R8 detection signal 106. This makes it possible to compensate with the R8 prediction signal 112 even if the RS detection signal 106 cannot be detected, thereby improving the reliability of data demodulation.

Figure 4 (B) shows the case where the R5 detection signal 106 is erroneously detected at the first 106', (B-1) shows the case where the counter 23 is not initialized with the R8 detection signal 106, and (B-2) shows the case where the RS is detected. This is a case where the signal 106 is used for initialization. At this time, in the former case, the R8 prediction signal 112 will be erroneously compensated, and demodulation will also start from the wrong position, resulting in an error. However, in the latter case, only the first block is demodulated at the wrong position, but from the second block onwards, it is demodulated at the correct position. On the other hand, Fig. 4(C) shows a case where the R8 detection signal 106 is not found at the correct position in a certain block, but the R8 detection signal 106' is found at the wrong position (the undetected R8 detection signal and the erroneous detection occur in the same block). (or when there is an increase/decrease in the PLL clock), (C-1) is the counter 2 with the R8 detection signal 106.
3 is not initialized, (C-2) is the R5 detection signal 10
This is the case when initialized with 6. In this case, there is no problem in the former case, but in the latter case, it becomes impossible to demodulate the missing RS prediction signal by two blocks. Therefore, by counting the disable time of the enable signal related to the demodulation timing gate signal 107 of the data demodulation operation,
A frame recovery gate signal is generated only when it is not activated for a period longer than a certain window, and a recovery pulse is sent to forcibly write data into the sector buffer memory and set the address to a predetermined address. Therefore, when demodulating data, there are two options: whether to initialize or not.
It is necessary to operate various types of means efficiently.

Whether or not to initialize the counter of the R8 prediction signal 112 with the R8 detection signal 106 can be determined as long as it is known whether the data demodulation is normal or not, and the selection can be easily made by using the R8 information 114 as a means for that purpose.

In other words, the counter 23 of the R8 prediction signal 112 is
is initialized with the R8 detection signal 106.

If detected, do not initialize. Also, R8
If normality is detected twice or more in the information 114, the reliability is further improved.

On the other hand, if the number of PLL clocks increases or decreases in units of one block, in the above case, once the normal state is recognized, the R5 prediction signal 112 will be output at the wrong position.
After that, demodulation may not be possible correctly.

That is, the R8 detection signal 106 and the R5 prediction signal 112 are
This occurs when the detection signal 106 is off. This will be explained using FIG. 5.

Figure 5 (A) shows that the number of PLL clocks in one block is R.
This shows a case where the width of the window for comparing the positions of the R8 detection signal 106 and the R8 prediction signal 112 is reduced by the width of the window. The counter 23 of the R8 prediction signal 112 has already been set to R
8 detection signal 106 causes a transition to a non-initialization mode. (When normal detection is recognized and the return mode signal is at “L” level), a mask gate signal 110 is generated to prevent the R8 prediction signal 112 from being initialized with the R8 detection signal 106 in the block. be done. If the PLL clock 104 decreases by the width of the window for comparing the positions of the R8 detection signal 106 and the R5 prediction signal 112 in the Nth block, the RS information 114 within the window is in the fourth state, that is, the R8 The detection signal 106 is not detected, the return mode signal is set to "H" level, and R8
A mode is set in which the counter 23 of the prediction signal 112 is initialized with the RS detection signal 106. Therefore, in the (N+1)th block, demodulation starts from the wrong position, but (N+2)
) block, R8 detection signal 106 and R8 prediction signal 1
12 counters 23 are initialized, demodulation operation is not activated in the (N+2)th block, and a recovery pulse is generated to set the sector buffer memory at a predetermined address.

Then, if the next R8 information 114 indicates normal detection,
The return mode is set to "L" level so that the counter 23 of the R8 prediction signal 112 is not initialized by the R8 detection signal 106.

Figure 5 (B) shows that the number of PLL clocks is R within one block.
This shows a case where the width is increased by the width of the window for comparing the positions of the R8 detection signal 106 and the R8 prediction signal 112. The counter 23 of the R8 prediction signal 112 has already been set to R
5 detection signal 106 (return mode signal is #L11 level), the R8 detection signal 10 is changed to the R8 prediction signal 112 in the block.
The mux gate signal 110 is generated so as not to be initialized at 6. Now at the Nth block, PLL clock 104 is R
When the width of the window for comparing the positions of the R8 detection signal 106 and the R8 prediction signal 112 increases, the R8 information within the window becomes the fourth state, that is, the R8 detection signal 106 is not detected, and the return mode is activated. The signal is set to uH level, and the mode is set in which the counter 23 of the R8 prediction signal 112 is initialized with the R8 detection signal. Therefore, (N+
1) In the second block, demodulation starts from the wrong position, but
Since the counter 23 of the R5 prediction signal 112 is initialized by the R8 detection signal 106 in the (N+1)th block, (N
+2) It is determined that the R3 information 114 is normally detected in the block, the return mode is set to It L # level, and the counter 23 of the R8 prediction signal 112 is not initialized with the R8 detection signal 106.

The above explanation deals with the case where the return mode goes to the "L" level in the middle of a sector, but the same thing happens even if it happens again at the beginning or in another block. In addition, the condition for returning the return mode from (# HII to it L 11) is that the first state of the R5 information 114 in the normal state is detected once, but this is detected twice or more consecutively. You can do this if you can find it.

Also, in this embodiment, an optical disc was used as an example, but
It goes without saying that the purpose of the present invention will not be lost if the medium records and reproduces information in sectors, such as magnetic disks and floppy disks.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, it is possible to detect bit slips caused by long burst errors existing on a disk during demodulation of data including a resynchronization signal for each block.

By memorizing the detection state of the resynchronization signal, it is possible to prevent increases and decreases in the PLL clock or frame slip phenomena, and reduce errors during demodulation of the obtained demodulated data. The effect it can have is huge.

[Brief explanation of drawings]

FIG. 1 is a demodulation block diagram in an embodiment of the present invention, and FIG. 2 is a timing diagram of a window signal. Figure 3 is a timing diagram of R5 information generation, Figure 4 is a timing diagram of a prediction signal of a resynchronization signal, Figure 5 is a timing diagram of a frame recovery mode signal, and Figure 6 is a sector format diagram including a resynchronization signal. It is. 1... Synchronization pull-in signal (SYNC), 2... Data mark (DM), 3... Re-synchronization signal (R8), 5
... Sector identifier (ID), 6... Optical disc, 7
. . . Photodetector, 8. Preamplifier, 9. Waveform equalization circuit. 10... Comparator, 11... Address reproduction circuit, 12... CPU, 13... Demodulation circuit, 14...
・PLL circuit, 15...Data mark detection circuit, 16
...Resynchronization signal detection circuit. 17... Demodulation timing gate signal generation circuit, 18
... Demodulation section, 19 ... RAM control circuit, 2
0...RAM, 21...Error correction detection circuit, 23.
...Counter, 24...Decoder, 25...Resynchronization position comparison circuit, 26...R5 information generation path, 100...
... Reproduction signal, 101... Binarized reproduction signal, 103.
... Demodulation command signal, 104 ... Regeneration clock, 105
...DM detection signal, 106...R8 detection signal, 10
7... Demodulation timing gate signal, 108... Demodulation data, 109... RAM write gate signal, 11
0...Mask gate signal, 111...Gate output,
112...R8 prediction signal, 113...Window signal, 114...R8 information.

Claims (1)

[Scope of Claims] 1. A demodulation circuit for reproducing data recorded on a recording medium having a sector structure and including a resynchronization signal for each block, comprising means for detecting a resynchronization signal from the reproduction signal; demodulation means for detecting the resynchronization signal from the signal and demodulating the data; means for storing the demodulated data for each block in a sector buffer memory; and determining the next resynchronization signal detection position from the already detected resynchronization signal. means for predicting, means for comparing the detected resynchronization signal position with the predicted resynchronization signal position, means for storing the detection state of the resynchronization signal obtained by the comparison means, and the resynchronization signal position in each block. According to the detection state of the synchronization signal, a bit shift operation is performed on the output data obtained from the demodulation means to re-demodulate the data, and when a block for which the resynchronization signal cannot be detected is detected from the reproduced signal, the block equivalent to one block is detected. forced data storage means for forcibly storing the data in a predetermined position of the sector buffer memory, and the detection state of the resynchronization signal is a resynchronization signal detection position where the resynchronization signal is expected to be detected. The first state is resynchronized at the same position, the second state is resynchronized at a position further than the expected resynchronization signal detection position, and the second state is resynchronized at a position later than the expected resynchronization signal detection position. A demodulation circuit having a third state in which the synchronization signal is synchronized and a fourth state in which the resynchronization signal is not detected at an expected resynchronization signal detection position. 2. The demodulation circuit according to claim 1, wherein the next resynchronization signal detection position is predicted by a counter from the detected resynchronization signal. 3. The demodulation circuit according to claim 2, wherein the counter is initialized by the detected resynchronization signal. 4. When the detected resynchronization signal is in the first, second, or third detection state, the counter is not initialized within the demodulation of one block of data. 4. The demodulation circuit according to claim 3, wherein the demodulation circuit is released. 5. The counter is initialized within the demodulation of one block of data when the resynchronization signal is detected twice or more and is in any of the first, second, and third detection states. 4. The demodulation circuit according to claim 3, wherein the demodulation circuit cancels this. 6. Even if the counter transitions to a non-initialized state during demodulation of one block of data, when the fourth state of the detection state is detected once, it is initialized by the resynchronization signal detected again. The demodulation circuit according to claim 4 or 5, characterized in that: 7. Even if the counter transitions to a non-initialized state during demodulation of one block of data, when the fourth state of the detection state is detected twice in succession, the counter is initialized by the resynchronization signal detected again. The demodulation circuit according to claim 4 or 5, characterized in that: