JP2589673B2 - Address data detection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device used as an external storage device of a computer, and more particularly to a direction of address data composition suitable for a recording medium with a high bit error rate, such as an optical disk, and its detection. Related to the device.

[Background of the Invention]

In a magnetic disk device conventionally used as an external storage device of a computer, data is written and read in units of data blocks called sectors. Therefore, at the beginning of each sector, an area for writing address data for specifying the sector is provided. A method of writing only this address data in the initial state of the disk and then specifying the sector by reading the address data in subsequent sector access is widely used (Interface 1984-5, No. 84, No. 84). "Hard Disk Drives and Controllers", published by CQ).

In such a system, even if no error occurs in the user data portion, if an error occurs in the address data portion and the address value cannot be read, the entire sector becomes unusable. It is necessary to reduce the bit error rate on the disk and increase the reliability.

On the other hand, even in an optical disk memory device capable of high-density recording as compared with a conventional magnetic disk, a function similar to that of a magnetic disk is required. Therefore, a method of writing address data at the head of each sector is also employed. (Nikkei Electronics 1983.11.21, Large-capacity optical disk file device capable of recording code information).

However, when comparing the bit error rate between the conventional magnetic disk and the optical disk, the former is 10 ⁻¹² or less, whereas the optical disk is as bad as 10 ⁻⁵ to 10 ^−6. By adding an ECC (error correction code) that is stronger than the ECC (error correction code) used for magnetic disks, the final bit error rate is improved.
However, it is difficult to add an effective ECC due to the short bit length of the address data part. ing.

However, this method causes a rise in the price of the disk, and there is a problem that there is no effective countermeasure against errors due to dust or scratches after shipping.

[Object of the invention]

An object of the present invention is to solve the above-mentioned problems of the prior art,
It is an object of the present invention to provide an address data configuration method and an apparatus for detecting address data, which make it impossible to detect address data due to an error in the address data and reduce the occurrence of unusable sectors caused by the error.

[Summary of the Invention]

The feature of the present invention is that the address data is double-recorded including the synchronization signal and the error detection code relating to the address data, and the two synchronization signals are combined with the address data and the error detection code at the time of reading. Thus, the number of undetectable occurrences of address data is reduced by performing detection by two error detection circuits in parallel.

(Example of the invention)

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a system block diagram when the present invention is applied to an optical disk device.

In the figure, 1 is an optical pickup for reading data on a disk or writing data on a disk, 2 is a head amplifier for amplifying the output of the optical pickup 1, and 3 is a digital amplifier for outputting the output of the head amplifier 2 to a digital level signal. A data separator circuit for performing conversion and clock recovery synchronized with data, 4 is an address signal detection circuit according to the present invention, 5 is a data writing circuit, 6 is a data reading circuit, 7
Is a control circuit, 8 is a host computer, and 20 is an address latch.

Such an optical disk device is composed of a host computer 8
Writes data input from the disk onto the disk, reads data from the disk as needed, and outputs it to the host computer 8.

The data format on the disc is divided into data blocks called sectors as shown in FIG. In each sector, an address data portion (pre-format portion) in which an address value indicating a value unique to the sector is recorded in advance.
9, a data section (an additional recording section) 10 into which data is written later. In the figure, 10a is a data portion in which data has already been added, and 10b is a data portion in which data has not yet been added.

FIG. 1 shows an example of the configuration of the address data section 9. In the figure, reference numeral 11 denotes a sector mark (SM) indicating the head of an address data part, that is, the head of a sector; 12, a pull-in signal (VFO) for synchronizing the clock of the clock reproducing part with subsequent data; Two synchronous signals (STNC1, STNC2), 14 and 14 'according to the present invention are also two addressless signals (ID), and 15, 15' are error detection codes (CRC). Reference numerals 50, 51, 52, and 53 denote a reproduction signal, a clock, an address signal, and a true / false signal, respectively, which will be described later.

As a general example of how to give an address signal, a method is used in which a disk is divided in the radial direction and this is called a track, and this one track is divided into a predetermined number to form a sector. Therefore, a sector is designated by a combination of a track number and a sector number.

When connected to a computer and used as an external storage device, it is required to be able to perform writing and reading in sector units, so that it is important to correctly detect an address signal. Therefore, as shown in FIG. 1, by recording the address data twice together with the synchronization signal and the error detection code, the probability that both will not be able to detect the address data by mistake at the same time is only recorded once, and Since the probability that address data cannot be detected becomes smaller, the number of sectors in which address detection becomes impossible can be reduced.

FIG. 4 shows a specific configuration diagram of the address signal detection circuit 4 shown in FIG.

In the figure, reference numeral 41 denotes a first synchronization detection circuit for detecting the first synchronization signal 13, reference numeral 42 denotes a second synchronization detection circuit for detecting the second synchronization signal 13 ', and reference numeral 43 denotes a connection to the optical disk. A demodulation circuit 44 for restoring a signal modulated so as to be suitable for recording is provided with an address signal 14 (14 ') and an error detection code 15 (1
5 '), a first error detection circuit 45 having the same input as the input, 45 is a second error detection circuit, and 46 is a detection address data based on error determination results 57, 60 of the first and second error detection circuits 44, 45. A decoder circuit for outputting a correct / incorrect signal 53 of the above and a switching signal 54 of a switching circuit to be described later, 47 is a first register for holding address data, 48 is a similar second register, and 49 is a first and second register 47. , 48 for selecting the data held in the memory and outputting the selected data to the subsequent circuit.

In the figure, reference numeral 50 denotes a reproduced signal from the optical disc;
Is a clock signal synchronized therewith, 52 is a detected address signal, 53 is a correct / incorrect signal of the address signal, and 54 is a switching signal. 57 and 60 are the first and second, respectively.
Is a signal representing the detection result of the error detection circuits 44 and 45 of
The details will be described later. Here, as the decoder circuit 46, for example, a circuit as shown in FIG. 6 can be used.

Next, the operation of this circuit will be described with reference to the time chart of FIG. When the first synchronization detection circuit 41 detects SYNC1 based on the reproduction signal 50 and the reproduction clock 51, the detection signal 54
(See FIG. 5) is supplied to a first error detection circuit 44.
The error detection circuit 44 uses the signal 54 as a reference for the first ID section.
Perform 14 error detections. Signal 56 is the operation block.

If the result is correct, the first error detection circuit 44
, The detection result (57) output from the terminal becomes “1”, a data latch pulse (58) appears, and the address data is held in the first register 47. This can be realized, for example, by inputting the detection result 57 to the differentiating circuit, extracting only the positive pulse of the differential output, and using this as the latch pulse 58 of the first register 47. If the data is incorrect, the detection result (57) becomes "0" and the data latch pulse (58) does not appear, so that the address data at this time is not held in the register 47.

This operation is similarly performed for the SYNC2 detection signal (55) in the second synchronization detection circuit 42.

Accordingly, the first register 47 holds the data of the two detected address data that has been detected, and if both are correctly detected, holds the second data. On the other hand, if both are not detected correctly,
The data held before the start of the sector detection is held as it is.

On the other hand, in the second error detection circuit 45, when the SYNC1 detection signal (54) is input, an error of the second address signal is detected by the detection clock (59) based on the input, and if the data is correct as a result. Detection result (60) is "1"
The data latch pulse (61) appears, and the second address data is held in the register 48. If the result is incorrect, the detection result (60) becomes “0” and the data latch (6
1) does not appear and address data is not retained. That is, since the second address data is detected using SYNC1 without using SYNC2, the second address data can be detected even if an error occurs in SYNC2 and the SYNC2 is not detected.

The decoder 46 finally determines whether the address data is correct or not and selects the registers 47 and 48 by the determination circuits 57 and 60 of the two error detection circuits 44 and 45. That is, when one of the first and second data addresses is correct or both are correct in the first error detection circuit 44, the address correct signal 53 outputs a "correct" signal, and the switching circuit 49 outputs the "correct" signal. The data held in the first register 47 is output.

If both address data in the first error detection circuit 44 are erroneous, but the address data is correctly detected in the second error detection circuit 45, the address correct / error signal 53 outputs a "correct" signal. Then, the switching circuit 49 outputs the data held in the second register 48.

Further, if all the detection results are erroneous, the address correct / wrong signal 53 outputs a signal of “wrong”. At this time, the address data 52 has no meaning.

As described above, according to the present invention, the second address data can be detected even if an error occurs in any one of the first synchronization signal, the address data, and the error detection code and the first address data cannot be detected. , The first address data can be detected even if an error occurs in any of the second synchronization signal, the address data, and the error detection code and the second address data cannot be detected. An error occurs at the boundary point of the second synchronization signal, the first address data becomes an error, and even if the second synchronization signal cannot be detected, the second address data is detected based on the first synchronization signal. be able to.

In the present invention, the case where the address data cannot be detected is a case where the address data is incorrect in the first and second data at the same time. However, the probability of occurrence of such a situation is very small considering the error occurrence probability of the optical disk. Since most of the errors are any one error, according to the present invention, the number of undetected sectors of the address data can be greatly reduced.

In the first synchronization signal and the second synchronization signal described in the present embodiment, both may be different patterns or the same pattern. Synchronous detection circuit if the same pattern
A time gate signal for distinguishing the first synchronization signal from the second synchronization signal is required instead of enabling sharing of 41 and 42, but does not affect the effect of the present invention.

〔The invention's effect〕

According to the present invention, even if an error occurs in one part of the double-written address data and the data cannot be correctly detected, the data can be correctly detected by the other address data. is there.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an address data section according to an embodiment of the present invention, FIG. 2 is a block diagram of an optical disk device using the address detection circuit of FIG. 1, and FIG. FIG. 4 is a block diagram showing an embodiment of an address detection circuit according to the present invention; FIG. 5 is a time chart for explaining the operation of the address detection circuit shown in FIG. 1; It is a circuit diagram. 13,13 '... first and second synchronization signals, 14,14' ... first,
Second address signal, 15, 15 '... first and second error detection codes, 41 ... first synchronization signal detection circuit, 42 ... second synchronization signal detection circuit, 44 ... first Error detection circuit, 45 ……
A second error detection circuit, 46, a decoder, 47, a first data register, 48, a second data register, 49, a switching circuit.

Claims (1)

(57) [Claims] 1. A data block for recording and reproducing data in a predetermined number of data units is composed of an address part for specifying the data block and a data part for recording and reproducing data, and the address part is composed of address data. An address data detection device for detecting address data from a data block sequence including a plurality of address data blocks recorded in the order of an address synchronization signal indicating a head, address data, and an address error detection code, comprising: a first address synchronization signal; , A second address synchronization detection circuit for detecting a second address synchronization signal, and a first address data based on the synchronization detection signal of the first address synchronization detection circuit. And checking the first address data with the first address error detection code and the second address. The second address data and second address error detection code for synchronization detection signal as a reference of the period detecting circuit second
A first error detection circuit for checking the address data of the second address data and a second address data and a second address error detection code based on a synchronization detection signal of the first address synchronization detection circuit. A second error detection circuit that holds the first address data when it is determined that the first address data is correct in the first error detection circuit, and holds the first address data when the second address data is determined to be correct. A first data register for holding the second address data, and a second data register for holding the second address data when the second error data is determined to be correct by the second error detection circuit. The test output of the first error detection circuit and the test output of the second error detection circuit are input to the first data register and the second data register. A decoder circuit for outputting a signal indicating a data register in which correct data is held among the data held in the first and second data registers, and a correct data among the first data register and the second data register according to an output of the decoder circuit. And a data switching circuit for selecting a data register that holds the address data.