JP3442945B2 - Synchronous circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in, for example, an optical disc reproducing system for optically reading and reproducing recorded data from a disc on which moving image data and audio data are compressed and encoded and recorded. The present invention relates to improvement of a synchronous circuit.

[0002]

2. Description of the Related Art As is well known, in recent years, not only audio data but also moving image data can be compressed and recorded on an optical disk having a diameter of 12 cm, which is the same as an audio CD (Compact Disk). ing. An example of this type of optical disc is a CD-ROM (Read Only Memory).
y) etc. are widespread in a wide range of fields from educational to karaoke.

In addition, at present, only moving image data corresponding to a movie for about 2 hours and audio data in eight different languages are compression-encoded and recorded at high density on an optical disc having the same diameter as a CD. In addition, an optical disc known as a DVD (Didital Video Disk), which is capable of recording sub-picture data representing subtitles in 32 different languages, has also been developed.

In various optical discs typified by such CD-ROMs and DVDs, the compression-coded moving image data sequence and audio data sequence are divided into units called sectors. Then, on the optical disc, a sector of moving image data and a sector of audio data are
Each is recorded as a data stream arranged in a time division manner.

Here, one sector is, as shown in FIG.
It is divided into 26 units called frames. Then, in FIG. 4, one sector is from top to bottom,
The left frame, the right frame, the left frame, the right frame, and so on are played in this order. Each frame in one sector is assigned a frame number such as 0th, 1st, ..., 25th frame according to the reproduction order.

Each frame is composed of a sync code sync and compression-coded moving image data or audio data. Of these, the sync code sync
Is composed of a specific code and a common code, and is classified into 8 types of sync0 to sync7 depending on the specific code.
The eight types of sync codes sync0 to sync7 are fixed in the arrangement shown in FIG. 4 in all sectors.

Such eight types of sync codes sync0 to sy
Due to the arrangement of nc7, sync code sync0-sync at playback
The start position of the sector and the frame number can be detected according to the order obtained. In addition,
All data of the structure shown in FIG. 4 has a structure in which bit synchronization is achieved not only in the same sector but also between sectors.

The moving image data and audio data recorded as described above are subjected to error correction processing in sector units and decoding processing in frame units by detecting the synchronization code sync during reproduction. To restore the original data. Therefore, in order to properly reproduce the moving image data and audio data recorded on the optical disc, the synchronization code sy
It is necessary to detect nc and accurately grasp the frame number.

FIG. 5 shows a sync code sync from the reproduced data string.
And a conventional synchronizing means for detecting the frame number. That is, the serial reproduction data string input to the input terminal 11 is supplied to the frame synchronization circuit 12. The frame synchronization circuit 12 detects the pattern of the synchronization code sync contained therein from the input reproduction data sequence and generates a detection synchronization signal.

A PLL (Phase Locked Loop) clock bit-synchronized with the reproduction data string is input to the input terminal 13. Then, the frame synchronization circuit 12 starts the input terminal 1 from the time when the detection synchronization signal is generated.
By counting the PLL clocks supplied to 3, the temporal position at which the next sync code sync is detected is predicted, and the presence or absence of the sync code sync is again detected near the predicted position.

In this case, when the sync code sync is detected at the predicted position, the frame sync circuit 12 counts the PLL clock again from the time when the sync code sync is detected, and the next time the sync code sync is detected. The operation of predicting is repeated. In addition, the frame synchronization circuit 12
Generates a pseudo sync signal at the predicted position when the sync code sync is not detected at the predicted position.

The detected synchronizing signal and the pseudo synchronizing signal output from the frame synchronizing circuit 12 are respectively supplied to the OR circuit 14 and subjected to a logical sum operation to generate a frame number counter clock. It
The frame number counter clock is supplied to the sector synchronization circuit 15 and counted to generate a frame number, which is taken out from the output terminal 16.

FIG. 6 shows the relationship between the pseudo sync signal and the detection sync signal output from the frame synchronization circuit 12, the frame number counter clock output from the OR circuit 14, and the frame number output from the sector synchronization circuit 15. Is shown. That is, the frame synchronization circuit 12 generates a detection synchronization signal at a constant cycle corresponding to the synchronization code sync when the synchronization code sync is stably detected from the reproduction data string.

In this case, the frame synchronization circuit 12 always obtains the sync code sync at the position where the sync code sync is predicted to be detected, so that the pseudo sync signal is controlled so as not to be generated. The pseudo sync signal shown by the dotted line in FIG.
The predicted position for detecting the presence or absence of the synchronization code sync is shown for convenience, and is not actually output.

Therefore, the OR circuit 14 generates a frame number counter clock that matches the detection synchronization signal. And this frame number counter clock is
The sector synchronization circuit 15 counts. In this case, the sector synchronization circuit 15 resets the count value at the head frame (0th frame) of the sector, and each frame number in one sector is generated here.

On the other hand, when the sync code sync is no longer detected in the reproduced data string, the frame sync circuit 12 uses the sync code sync detected last as shown in FIG.
As shown in, a pseudo sync signal is generated at a position where the sync code sync is expected to be obtained. At this time, the frame synchronization circuit 12 is set so as to be able to detect the presence or absence of the synchronization code sync not only in the predicted position but in the entire area.

Therefore, if the sync code sync is not detected, only the pseudo sync signal is output from the frame sync circuit 12, and the OR circuit 14 generates the frame number counter clock that matches the pseudo sync signal. Then, the frame number is generated by counting the frame number counter clock in the sector synchronization circuit 15.

By the way, in FIG. 7, the frame synchronization circuit 1 is operated at an arbitrary time T2 after the pseudo sync signal is generated at time T1 and before the next pseudo sync signal is generated.
2 detects the sync code sync and generates a detection sync signal. Then, the frame synchronization circuit 12 operates so as to predict the position at which the presence or absence of the synchronization code sync is detected from the time when the detection synchronization signal is generated, and resynchronization is performed there.

However, in the conventional synchronizing means as described above, after the frame number is counted from N + 1 to N + 2 based on the pseudo synchronizing signal generated at time T1,
Since the frame number is erroneously counted from N + 2 to N + 3 based on the detection synchronization signal generated at time T2, the frame number after resynchronization does not match the frame number (actual frame number) actually reproduced. The problem of disappearing is occurring.

[0020]

As described above, in the conventional synchronizing means, when resynchronization is performed, the frame number is erroneously counted and does not match the number of the frame actually reproduced. However, there is a problem in that it is impossible to accurately perform the error correction processing and the decoding processing in units of frames, which makes it impossible to perform a highly reliable reproducing operation.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to prevent the frame number from being erroneously counted at the time of resynchronization so that an accurate frame number can be always obtained, and reliability is improved. It is an object of the present invention to provide an extremely good synchronization circuit that can contribute to performing a high reproduction operation.

[0022]

A synchronizing circuit according to the present invention has a synchronizing signal having a plurality of types of synchronizing codes and is divided into a plurality of sector units each of which is composed of a predetermined number of frames containing the synchronizing signal. Each of the frames that make up one sector
If the frames are numbered according to the playback order,
In both cases, depending on the code included in the sync signal,
The first frame is detected based on the sync signal detecting means for detecting the sync signal and generating the detection sync signal from the digital data string capable of detecting the head frame, and the detection sync signal output from the sync signal detecting means. It predicts the temporal position of the synchronization signal is generated, when no is obtained synchronization detection signal at the predicted position, and the pseudo synchronization signal generating means for generating a pseudo-sync signals, synchronization detection signal outputted from the synchronizing signal detecting means Alternatively, the pseudo sync signal generated by the pseudo sync signal generating means is counted, and the first frame in one sector is detected.
Were by the count value is reset in a state, a frame number generating means for generating a frame number, a pseudo synchronizing signal generating means by one time false sync signal is generated et al
In pre Me set period of time, synchronization detection signal outputted from the synchronization signal detection means includes a controlled Ru control means so as not to be subjected to the generation of the frame number by the frame number generating unit, by the pseudo synchronizing signal generating means pseudo Sync signal is emitted
After the preset period of time from the time of birth
Then, the detected sync signal output from the sync signal detection means
Is the frame number generated by the frame number generation means
Of the detected sync signal output from the sync signal detecting means.
The frame number is determined by determining the correspondence with the type of period code.
Is configured to decide whether or not to use for playback
And a frame number correcting means .

According to the above-mentioned configuration, the detection synchronization signal output from the synchronization signal detecting means is changed to the frame number generation means for outputting the frame number by the frame number generating means for a predetermined fixed period from the time when the pseudo synchronization signal is generated. Since it is not used for generation, even if the detection synchronization signal is suddenly output and resynchronization is performed in a state where the pseudo synchronization signal continues to be generated, the frame number generated by the frame number generation means is The value generated based on the synchronization signal remains unchanged.

Therefore, it is divided into a plurality of sector units,
Each frame that composes one sector is
Plays a digital data string that has a system number
When, during resynchronization miscount of the frame number is prevented, always such to be able to obtain accurate frame number Runode, it can perform reliable high reproducing operation
To become.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In FIG. 1, the serial reproduction data string supplied to the input terminal 17 is the sync code detection circuit 18 that constitutes the frame sync circuit 18.
is supplied to a. The sync code detection circuit 18a detects a pattern of the sync code sync from the input reproduction data string and generates a detection sync signal.

The detected synchronizing signal output from the synchronizing code detecting circuit 18a is supplied to the synchronizing signal predicting circuit 18b, and the frame number correcting circuit constituting the sector synchronizing circuit 19 connected to the subsequent stage of the frame synchronizing circuit 18. 19a. Of these, the synchronization signal prediction circuit 18b operates so as to output the input detection synchronization signal as it is.

A PLL clock bit-synchronized with the reproduced data string is supplied to the frame synchronization circuit 18 through an input terminal 20. Then, the synchronization signal prediction circuit 18b counts the PLL clock from the time when the detection synchronization signal is input, predicts the temporal position at which the next detection synchronization signal is input, and detects again near the predicted position. It is detected whether or not a sync signal is input.

In this case, when the synchronization signal predicting circuit 18b receives the detection synchronization signal at the predicted position, it counts the PLL clock again from the input time point and the next detection synchronization signal is input in time. The operation of predicting the position is repeatedly executed. Then, the synchronization signal prediction circuit 1
When the detection sync signal is not input at the predicted position, 8b generates a pseudo sync signal at the predicted position.

Further, the synchronizing signal predicting circuit 18b generates a driving signal to the clock control signal generating circuit 18c when the pseudo synchronizing signal is generated. The clock control signal generation circuit 18c normally outputs a clock control signal of H (high) level, but when a drive signal is input, the clock control signal of L (low) level is output for a certain period from that point. Works to output.

The detected sync signal output from the sync signal predicting circuit 18b and the clock control signal output from the clock control signal generating circuit 18c are supplied to an AND circuit 18d to be subjected to a logical product operation process. After that, the frame number counter clock is generated by being supplied to the OR circuit 18e together with the pseudo synchronization signal output from the synchronization signal prediction circuit 18b and subjected to the logical sum operation processing.

In this case, if the sync code detecting circuit 18a stably detects the sync code sync in the reproduced data sequence and outputs the detection sync signal, the sync signal predicting circuit 18b receives the detection sync signal. Since the detection synchronization signal is always input at the predicted position, the pseudo synchronization signal is not generated and the drive signal is not generated accordingly.

Therefore, the clock control signal generation circuit 18
Since the clock control signal of H level is generated from c, the gate of the AND circuit 18d is opened. That is, from the AND circuit 18d, the synchronization signal prediction circuit 18b
The detection synchronization signal output from is output as it is. After that, the detection synchronization signal output from the AND circuit 18d becomes the frame number counter clock via the OR circuit 18e.

The frame number counter clock is supplied as an output of the frame synchronizing circuit 18 to the frame number creating circuit 19b constituting the sector synchronizing circuit 19. The frame number creating circuit 19b generates a frame number by counting the input frame number counter clock. This frame number is taken out from the output terminal 21 as the output of the sector synchronization circuit 19.

Here, the frame number correction circuit 19a is used.
Operates to reset the count value of the frame number creating circuit 19b to 0 when the input detection sync signal corresponds to the sync code sync0. Therefore, the count value is reset at the head frame (0th frame) of each sector, and each frame number in one sector is generated here.

FIG. 2 shows a pseudo sync signal and a detection sync signal output from the sync signal prediction circuit 18b, a clock control signal output from the clock control signal generation circuit 18c, and a frame number counter output from the OR circuit 18e. The relationship between the clock, the frame number output from the frame number generation circuit 19b, and the number of the frame actually reproduced (actual frame number) is shown.

That is, the synchronization code detection circuit 18a
When the sync code sync is no longer detected from the reproduced data sequence by the sync signal prediction circuit 18b, the sync signal prediction circuit 18b pseudo-syncs to the position predicted to receive the detection sync signal based on the last input sync signal. Generating a signal. At this time, the synchronization signal prediction circuit 18b is set so as to be able to detect the detection synchronization signal not only in the predicted position but in the entire area.

Therefore, if the detection sync signal is not input from the sync code detection circuit 18a, the sync signal prediction circuit 1
Only the pseudo sync signal is output from 8b, and the OR circuit 18
A frame number counter clock corresponding to the pseudo sync signal is generated from e. Then, the frame number is generated by counting the frame number counter clock in the frame number creating circuit 19b.

In FIG. 2, the sync code detection circuit 1 is generated at an arbitrary time T2 after the pseudo sync signal is generated at time T1 and before the next pseudo sync signal is generated.
It is assumed that 8a detects the sync code sync and generates a detection sync signal. Then, the synchronization signal prediction circuit 18b operates so as to predict the position at which the next input of the synchronization detection signal is detected from the time when this detection synchronization signal is input, and resynchronization is performed there.

In this case, the sync signal predicting circuit 18b generates a drive signal each time a pseudo sync signal is generated. Therefore, the clock control signal output from the clock control signal generation circuit 18c is set to the L level for a certain period every time the drive signal is input. Then, during the L level period of the clock control signal, the gate of the AND circuit 18d is closed.

Therefore, from time T1 to time T2, which is within the period in which the clock control signal is at the L level.
When the detection synchronization signal is output from the synchronization signal prediction circuit 18b, the detection synchronization signal is blocked by the AND circuit 18d and is not supplied to the OR circuit 18e.
The detected sync signal output from the sync signal prediction circuit 18b in 2 does not function as the frame number counter clock.

As a result, as shown in FIG.
Even if the resynchronization is performed in the frame number generation circuit 19b.
The frame number counted at is not incremented, and remains the value N + 2 counted based on the pseudo synchronization signal at time T1. For this reason, erroneous counting of frame numbers is prevented during resynchronization, and an accurate frame number can always be obtained.

FIG. 3 shows an example in which the operation of the above embodiment is partially modified. That is, as described above, eight types of sync codes sync0 are included in one sector.
~ Sync7 exists. Therefore, it is possible to estimate the position of the currently reproduced frame, that is, the frame number, depending on the type of the synchronization code sync detected at the time of resynchronization.

Further, in the resynchronization, the difference between the frame number counted by the frame number generating circuit 19b and the number of the actually reproduced frame (actual frame number) is actually within one frame. In most cases. From these facts, the position of the frame at the time of resynchronization, that is, the frame number can be determined almost accurately.

Therefore, based on the pseudo sync signal generated at time T1, the frame number counted by the frame number creating circuit 19b is "1", and the detected sync signal obtained at time T2 thereafter is If it corresponds to the synchronization code sync5, it can be determined that the counted frame number “1” is very likely to be a correct value.

This judgment is made by the frame number correction circuit 1 described above.
9a based on the frame number output from the frame number generation circuit 19b and the sync code sync of the detection sync signal output from the sync code detection circuit 18a. Then, the frame number correction circuit 19a
When the frame number and the type of the sync code sync correspond correctly, a control signal is generated in the clock control signal generation circuit 18c.

At this time, the clock control signal generation circuit 18
c sets the clock control signal to the L level, and the AND circuit 1
The gate of 8d is closed. Therefore, even if resynchronization is performed at time T2, the count value of the frame number creating circuit 19b is not incremented and remains the value "1" counted based on the pseudo synchronization signal at time T1, It is possible to prevent erroneous counting of frame numbers.

As still another operation example, the operation described in FIG. 2 and the operation described in FIG. 3 can be combined. First, as described with reference to FIG. 2, the detection sync signal is obtained by closing the gate of the AND circuit 18d for a predetermined period from the time when the sync signal prediction circuit 18b generates the pseudo sync signal. However, do not let it be used for frame number generation.

Then, after the above-mentioned fixed period ends,
As described in FIG. 3, the frame number correction circuit 19a
Determines the correspondence between the frame number generated by the frame number generation circuit 19b and the type of the sync code sync of the detection sync signal output from the sync code detection circuit 18a, and the obtained detection sync signal is framed. It can also be configured to decide whether or not to use it to generate a number.
It should be noted that the present invention is not limited to the above-described embodiments, and can be variously modified and implemented without departing from the scope of the invention.

[0049]

As described above in detail, according to the present invention,
A frame number is prevented from being wrongly counted at the time of resynchronization, an accurate frame number can always be obtained, and an extremely good synchronization circuit that can contribute to performing a reliable reproduction operation is provided. be able to.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a synchronizing circuit according to the present invention.

FIG. 2 is a timing chart shown to explain the operation of the embodiment.

FIG. 3 is a timing chart shown for explaining a modified example of the operation of the embodiment.

FIG. 4 is a diagram shown for explaining the structure of one sector.

FIG. 5 is a block diagram showing a conventional synchronizing means.

FIG. 6 is a timing chart shown for explaining the operation of the conventional means.

FIG. 7 is a timing chart for explaining a problem of the conventional means.

[Explanation of symbols]

11 ... Input terminal, 12 ... Frame synchronization circuit, 13 ... Input terminal, 14 ... OR circuit, 15 ... Sector synchronization circuit, 16 ... Output terminal, 17 ... Input terminal, 18 ... Frame synchronization circuit, 19 ... Sector synchronization circuit, 20 ... Input terminal, 21 ... Output terminal.

Claims (5)

(57) [Claims] 1. A synchronization signal having a plurality of types of synchronization codes.
It has, respectively divided into a plurality of sectors composed of a predetermined number of frames including a synchronous signal, structure one sector
Each frame that is created has a frame number according to the playback order.
A synchronization code attached to the synchronization signal and included in the synchronization signal.
The sync signal detecting means for detecting the sync signal and generating the detection sync signal from the digital data string in which the first frame in one sector can be detected by the sync signal detecting means and the sync signal detecting means for outputting the sync signal. A pseudo sync signal generating means for generating a pseudo sync signal when the temporal position at which the detection sync signal is generated next is predicted, and the detection sync signal is not obtained at the predicted position; Detection sync signal output from the means or pseudo sync signal generated by the pseudo sync signal generating means
And the first frame in one sector is detected
By the count value is reset in a state, a frame number generating means for generating a frame number, the predetermined period pseudo synchronization signal is set when either et pre Me generated by the pseudo synchronizing signal generating means, the synchronization signal synchronous detection signal output from the detecting means, the pseudo-synchronization signal is generated by the frame number and the controlled Ru control means so as not to be subjected to the generation of the frame number by generation means, said pseudo synchronizing signal generating means
After a preset period of time
Is a detected sync signal output from the sync signal detection means.
Is the frame number generated by the frame number generation means.
Signal and the detection synchronization signal output from the synchronization signal detecting means.
Of the synchronization code type of the
System to determine whether to use it for playing the
And a frame number correcting means that is formed. 2. The fixed time set by the control means is
2. The cycle is set to be shorter than the cycle of the pseudo sync signal generated by the pseudo sync signal generating means.
The described synchronizing circuit. Wherein said control means from the time the pseudo-synchronization signal is generated by the pseudo synchronizing signal generating means, for a preset predetermined time, the detection sync signal outputted from said synchronizing signal detecting means, wherein 2. The synchronizing circuit according to claim 1, further comprising gate means for cutting off supply to the frame number generating means. 4. A plurality of types of synchronization signals are prepared,
Each frame in the sector includes a preset type of sync signal, and the control unit sets the frame number to the type of the sync signal detected by the sync signal detection unit. The detection synchronization signal output from the synchronization signal detection means is controlled so as not to be used for generation of the frame number by the frame number generation means in a state in which the frame number generated by the generation means corresponds. The synchronous circuit according to claim 1. Wherein said control means from the time the pseudo-synchronization signal is generated by the pseudo synchronizing signal generating means, for a preset period of time, the synchronization detection signal outputted from said synchronizing signal detecting means, wherein After controlling not to use for the frame number generation by the frame number generation means,
The type of sync signal detected by the sync signal detecting means,
Controlling that the detection synchronization signal output from the synchronization signal detection means is not used for generation of the frame number by the frame number generation means in a state in which the frame number generated by the frame number generation means corresponds. The synchronous circuit according to claim 4, which is characterized in that.