JPH05189877A - Digital signal reproducer - Google Patents

Abstract

PURPOSE:To realize a frame synchronizing signal compensating circuit without requiring a high capacity memory relay and the like by reproducing output signals from a gate circuit and a pulse generating circuit as synchronizing signals. CONSTITUTION:A reproduced digital signal is inputted through an input terminal 21 into a detecting circuit 22 and a detected frame synchronizing signal SFo is inputted into a gate circuit 23. The circuit 23 receives a gate signal PW from an OR gate 24 and delivers a detection signal SFW of the signal SFo to an OR gate 25 and the clear terminal of a counter 26. The counter 26 receives a clock pulse from a clock generator 27 and delivers a carry pulse SFC to the gate 25. A detector 28 detects a count lower by 3 than the count N of frame period to set an FF 30 whereas a detector 29 detects the count for three bits and resets the FF 30. A counter 31 receives the signal SFW and pulses detected through the detector 29 and delivers an High SL signal to the gate 24 upon reaching a predetermined count.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for a digital signal recorded in a base band which does not depend on a carrier modulation system such as AM modulation or FM modulation, and particularly to a compensation circuit section for a frame synchronization signal (block synchronization signal). Regarding

[0002]

2. Description of the Related Art For example, when an audio signal is a digital PC
There is known an apparatus which is converted into M and recorded on a disc, and the recorded digital PCM audio signal is reproduced from the disc. In the case of this PCM audio disc recording / reproducing apparatus, when recording a PCM audio signal, a method of recording in a base band that does not depend on a carrier modulation method such as AM modulation or FM modulation is adopted. In this case, a modulation method of a run length limited code is usually used. According to this modulation method, the minimum inversion interval between two data transitions with respect to "0" or "1" data is lengthened to improve recording efficiency, and the maximum inversion interval is shortened to provide a self-clock on the reproducing side. It is intended to facilitate.

By the way, when recording and reproducing a digital signal, in order to facilitate error correction and other processing of the digital signal, a plurality of samples are divided into blocks, and each block is processed. The length of one block is treated as one frame period in a digital audio disc. Then, a frame synchronization signal (block synchronization signal) is inserted into the head portion of the data for each block, and is used as a mark for each block.

In this case, as the frame synchronization signal, the maximum inversion interval is set to 2 by taking advantage of the fact that the modulation output in which the maximum inversion interval is continuous does not appear in normal modulation.
A bit pattern that is continuous one time, that is, a section of "1" continues for the maximum inversion interval, and then a section of "0" continues for the maximum inversion interval is used as the frame synchronization signal.

As described above, the frame synchronizing signal is detected on the reproducing side, and the subsequent data is appropriately processed by detecting the frame synchronizing signal. However, for the following reasons, this frame is processed. In some cases, the sync signal may not be detected correctly, and a compensation circuit for the frame sync signal is generally provided on the reproducing side.

That is, the frame synchronization signal may be lost due to, for example, a scratch on the disk.
There is also a case where pulse-like noise similar to the frame synchronization signal is mixed into the reproduction signal, and this is erroneously reproduced as the frame synchronization signal, resulting in an error in the subsequent processing. Furthermore, in a search mode such as the beginning of an audio signal, the frame sync signal is not detected, but if the frame sync signal is not obtained immediately after this search mode ends, the search mode is switched to the normal playback mode. After that, it will take some time for a stable reproduction signal to be obtained. The cycle of the frame synchronization signal may change due to various reasons, and it is necessary to correct it.

As such a frame synchronization signal compensating circuit, the one shown in FIG. 5 is conventionally known.

That is, in FIG. 5, the reproduced digital signal through the input terminal 1 is supplied to the register 2. The register 2 has a number of stages of n bits corresponding to the length of the frame synchronization signal, and n-bit parallel data is supplied to the frame synchronization signal detection circuit 3 by this register, and the frame synchronization signal of the above-mentioned bit pattern is supplied. Are detected by matching the patterns.

The output of the register 2 is supplied to the memory 4 of data for one block, and all the data within one frame period, that is, one block is written in the memory 4. When all the data for one block is written in the memory 4, each data is supplied from the memory 4 to the register 5. That is, memory 4
From this, data delayed by one frame period is obtained, and this data is supplied to the register 5. Like the register 2, the register 5 also has n-bit stages, and n-bit parallel data is supplied to the frame synchronization signal detection circuit 6 to detect the frame synchronization signal in the same manner as described above.
Further, after the output of the register 5 is supplied to the memory 7 for one block of data and delayed by one frame period,
It is supplied to the register 8. This register is also similar to the registers 2 and 5, and the n-bit parallel data from this register is supplied to the frame synchronization signal detection circuit 9, and the frame synchronization signal is detected with a delay of two frame periods from the input data. ..

The frame sync signal detection signals F0 and F from the frame sync signal detection circuits 3, 6 and 9 are detected.
When 1 and F2 are supplied to the majority logic circuit 10 and two or more signals among the three signals F0, F1 and F2 are in phase with each other at the time of occurrence, the time of coincidence and the output signal FA are The majority logic of being obtained is taken in this. The rotation speed of the disk is stable, and the frame sync signal is stable at the correct frame cycle.
9 is obtained, the phases of the output signals of the detection circuits 3, 6, 9 are in agreement, and the majority logic circuit 10
Therefore, the output signal FA is always obtained in the frame period.

When two or more consecutive frame period signals are lost due to dropout, the signals F0, F1 and F2 are lost.
, The phase of two or more signals will not match at the time of the dropout, so that the output signal FA from the majority logic circuit 10 cannot be obtained at that time.

The clock pulse CP from the clock generator 13 is supplied to the clock terminal of the counter 11. The counter 11 generates a carry pulse FC when counting the clock pulse CP from the clock generator 13 for one frame period, and the carry pulse FC becomes a signal of a frame period. Therefore, even when the signal from the majority logic circuit 10 cannot be obtained, that is, even when the frame synchronization signal having the correct period cannot be obtained, the signal of the frame period is obtained from the counter 11. If a frame synchronization signal having a correct cycle is obtained from the majority logic circuit 10, the counter 1 is activated by the frame synchronization signal.
Since 1 is reset, the carry pulse FC also becomes a signal having the same phase as the detected frame synchronization signal.

This carry pulse FC is the OR gate 12
Is supplied to the other input terminal of. Therefore OR gate 1
If the frame synchronization signal from the majority logic circuit 10 is correct from 2, the frame synchronization is taken out as it is, and if a signal is not obtained from the majority logic circuit 10 due to dropout or the like, an output carry pulse from the counter 11 is output. FC will then be available at the output 14.

Reference numeral 15 is an output end of PCM audio data.

The operation of this circuit will be further described with reference to a time chart.

In order to obtain a reproduced digital signal, it is necessary to bit-synchronize the signal extracted from the disk with a clock signal synchronized with this signal. In this bit synchronization circuit, the relative phase between the clock signal and the reproduced signal is obtained. If there is a deviation, a cycle slip phenomenon occurs in which it is omitted or increased by one cycle due to the integration. In the normal reproduction mode, the frequency error of the variable frequency oscillator of the PLL circuit and the time constant of the low pass filter of the bit synchronizing circuit are selected, and the time error caused by the cycle slip is suppressed to about ± 1 to 2 bits. ing.

FIG. 6 shows the cycle slip phenomenon.
The respective signals are shown when the phenomenon of shortening the cycle of the frame synchronization signal occurs and when dropout occurs.

That is, FIGS. 6A, 6B and 6C show the output signals F0, F1 and F2 of the frame sync signal detecting circuits 3, 6 and 9, respectively. The output signal F0 of the frame synchronization signal detection circuit 3 is a detection signal obtained by detecting the frame synchronization signal from the reproduction signal from the input terminal 1, and the output signal F1 of the frame synchronization signal detection circuit 6 is a state in which it is delayed by one frame period. And the output signal F2 of the frame synchronization signal detection circuit 9 is a signal delayed by one frame period.

In this case, the cycle of the third and fourth frame sync signals in FIG. 6A is shortened by the cycle slip, and the seventh and eighth block sync signals in FIG. 6A are missing due to dropout. This is the case. Further, in FIG. 6, a cycle indicated by a circle is a regular frame cycle, and a cycle indicated by a cross is an incorrect cycle.

In this case, as is clear from FIG.
In the portion where the cycle slip has occurred, the output signal FA of the majority logic circuit 10 is the signal from the frame synchronization signal detection circuit 6 for the fourth frame synchronization signal detection circuit as shown in FIG. Since F1 and the signal F2 from the frame synchronization signal 9 have the same phase, it is obtained at this point, while for the fifth frame synchronization signal, the phases of the signal F0 and the signal F1 are the same.
It will be taken out at this point.

Since the counter 11 is reset by the output of the majority logic circuit 10, the counter 11 obtains the signal FC as shown in FIG. In FIG. 6E, the signal of the fifth frame period is not obtained from the counter 11 because the period between the fourth and fifth periods is shorter than the frame period, the carry pulse FC from the counter 11 is counted. This is because the counter 11 is reset by the pulse from the majority logic circuit 10 before the above is obtained.

The OR gate output of the output FA of the majority logic circuit 10 and the output FC of the counter 11 is supplied to the terminal 14.
As the output signal FG of the frame synchronization signal, the one shown in FIG. In this case, it will be apparent that the frame synchronization signal in the dropout period is obtained by interpolating the carry pulse of the frame period obtained from the counter 11.

FIG. 7 shows a case where a cycle slip occurs between the third frame synchronization signal and the fourth frame synchronization signal, and the length thereof becomes longer than one frame period. This is an example of a case where an out occurs. In this case, the signals F0, F1 and F2 are shown in FIGS. A, B and C, respectively, and the signals FA, FC and
FG is shown in D, E, and F of FIG.

In the case of this example, since the length of the cycle slip is longer than one frame period, it is not reset before the carry pulse is obtained in the counter 11 as in the example of FIG. As shown in E,
Although the carry pulse of the frame period is obtained, the counter 11 is reset by the pulse FA from the majority logic circuit 10 at a time point between the obtained carry pulse and the next carry pulse. It corresponds to, that is, it is larger than one frame period. Therefore, the signal FG obtained at the terminal 14 is as shown in FIG.

FIG. 8 shows a case in which noise in the reproduced signal is mixed in as a pseudo frame synchronizing signal and the reproducing apparatus is in the search mode, and the frame synchronizing signal is detected in the frame synchronizing signal detecting circuits 3, 6 and 9 during the search mode. Is not detected. 8A, B, C and D, E, F show signals F0, F1, F2 and FA, as in FIGS.
These are FC and FG, respectively.

In this case, the pulses mixed in as the pseudo-synchronous signal do not overlap with each other in the positions of the signals F0, F1 and F2, so the output signal FA of the majority logic circuit 10 is as shown in FIG. It is obtained with this pseudo sync pulse removed.

Since the reproducing apparatus is in the search mode, the signals of the frame cycle are sequentially obtained from the counter 11 during the period when the frame synchronizing signal is not obtained, and the signals are obtained at the terminal 14. After the end of the search mode, the majority decision logic circuit 10 outputs the output pulse FA at the position of the second frame synchronization signal counted after the end of the search mode. Will be reset before the carry pulse is obtained. Therefore,
As shown in FIG. 6E, the period during this period is longer than one frame period, but the signal as shown in FIG. That is, a signal with a correct frame period is output immediately after the search mode ends.

As described above, a substantially correct frame synchronization signal is obtained by compensation in the case of an abnormal condition such as a cycle slip or a search mode, or the inclusion of dropout or noise.

[0029]

By the way, in this conventional circuit, a memory is required, and this memory needs to be high-speed, and since a majority logic circuit is used, each pseudo frame sync pulse has one pulse. When it is possible to obtain continuously at the same position of the frame period,
There was an inconvenience that this could not be removed.

The present invention intends to propose a circuit capable of eliminating the above drawbacks.

[0031]

SUMMARY OF THE INVENTION The present invention is modulated by a run length limited code and is divided into blocks for every unit time, and does not appear in the normal modulation of the run length limited code for this block unit data. An apparatus for reproducing a digital signal in which a bit pattern is added as a synchronization signal, the detection circuit 22 detecting the synchronization signal from the reproduced digital signal, and the detection signal of the synchronization signal from the detection circuit 22 are gated. Of the gate circuit 23, the pulse generation circuit 26 that is cleared by the output signal of the gate circuit 23 and that generates a pulse by counting the period of one block, and the period of one block that is counted by the pulse generation circuit 26. Form a window pulse with a pulse width of some period before and after the timing And supplies the window pulse to the gate circuit 23, a pulse width period, the gate circuit 23 opens and forms a window pulse forming circuit 24,28,29,30
And when a signal of a block cycle obtained based on the output signal of the pulse generation circuit 26 is counted as a clock while being cleared by the output signal of the gate circuit 23, and the count value becomes equal to or greater than a preset value. , A monitoring circuit 31 forcibly releasing the gate circuit 23, and an output signal of the gate circuit 23 and the pulse generation circuit 2
The output signal of No. 6 is reproduced as a synchronizing signal.

[0032]

According to the structure of the present invention, the sync signal is detected from the reproduced digital signal, and the pulse generation circuit 26 is cleared by the output signal obtained by gating the detection signal of the sync signal, and the block A pulse is generated by counting the period, a window pulse having a pulse width of a slight period part before and after the timing of the period of one block counted by the pulse generation circuit 26 is formed, and this window pulse is supplied to the gate circuit 23. Supply, pulse width section, gate circuit 23 is opened, pulse generation circuit 26
The signal of the block period obtained on the basis of the output signal of is counted as a clock, and when the count value exceeds a preset value, the gate circuit 23 is forcibly released and the output signal of the gate circuit 23 is And the output signal of the pulse generation circuit 26 is reproduced as a synchronization signal.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a frame synchronization signal compensating circuit according to the present invention will be described below with reference to the drawings.

First, the following points are taken into consideration in the present invention.

That is, the cycle slip that occurs in one reproduction signal is usually about ± 1 to 2 bits, which is extremely small with respect to the frame period. 2 The pattern of the frame synchronization signal is usually special. Therefore, it is necessary to have a relatively safe area before and after the pattern detection for frame sync signal detection. In many random data sequences, the occurrence probability of the same pattern is 0 or very small unless dropouts or pseudo sync signals are mixed.
Is.

FIG. 1 is an example of a system diagram of a compensation circuit according to the present invention, in which a reproduced digital signal through an input terminal 21 is supplied to a frame sync signal detection circuit 22. The frame synchronization signal detection circuit 22 detects a signal having the same bit pattern as the frame synchronization signal from the digital signal sequence as in the above-described example, and the frame synchronization signal detected by this circuit 22 is supplied to the gate circuit 23. To be done. The output signal of the OR gate 24 is supplied to the gate circuit 23 as a gate signal. In this case OR gate 2
As will be described later, the gate signal, which is the output signal of No. 4, is a window pulse having a pulse width of about ± 3 bits with respect to the normal frame sync signal occurrence position.
Therefore, when the frame sync signal is detected by the detection circuit 22 at the correct position, the detection signal SFO is obtained through this gate circuit 23.

The detection signal SFW of the frame synchronization signal obtained through the gate circuit 23 is supplied to one input terminal of the OR gate 25 and the clear terminal of the counter 26. A clock pulse CP from a clock generator 27 is supplied to the clock terminal of the counter 26. The clock generator 27 is adapted to be synchronized with the clock component of the reproduced signal, and for example, a PLL circuit is used. Therefore, the carry pulse SFC of the frame period synchronized with the reproduction signal is obtained from the counter 26. The frame cycle signal obtained from the counter 26 is supplied to the other input terminal of the OR gate 25.

The output clock of the clock generator 27 is also used as a clock for detecting the frame synchronization signal.

The gate signal PW of the gate circuit 23 is formed as follows based on the count value output of the counter 26.

That is, when the count value of the counter 26 becomes smaller than the count value N corresponding to the frame period by the maximum value of cycle slip, for example, the number corresponding to 3 bits of data, the detector 28 detects it.
The flip-flop circuit 30 is set by the detection output. The count value of the counter 26 is 3 of the data.
When the value corresponding to the bit is reached, it is detected by the detection circuit 29, and the flip-flop circuit 30 is reset by the detection output. Considering that the counter 26 is cleared by the signal SFW of the frame period, the flip-flop circuit 30 rises at a position of 3 bits before the position of the frame synchronization signal and is delayed by 3 bits from the position of the frame synchronization signal. A falling signal is obtained, and this is supplied to the gate circuit 23 through the OR gate 24 as the gate signal PW.

When the phase of the frame sync signal and the output carry pulse SFC of the counter 26 are out of phase, the gate circuit 23 cannot obtain the detection signal SFW of the frame sync signal. In this way, the counter 26 is forcibly cleared so that the phases of both counters match.

That is, 31 is a monitoring counter for detecting the state. The clear terminal of the counter 31 is supplied with the detection signal SFW of the frame synchronization signal obtained from the gate circuit 23, and the clock terminal is supplied with the output pulse of the detector 29.

In this case, since the counter 26 constantly counts the clock pulse CP, the detector 29 obtains a pulse at a frame period, which is the counter 3
Although it is counted as 1, the detection signal SFW of the frame synchronization signal is supplied to the clear terminal of the counter 31 in one frame period while the detection signal of the frame synchronization signal is obtained from the gate circuit 23. Therefore, the counter 31 is cleared each time one pulse from the detector 29 is counted, and the count value of the counter 31 does not advance.

On the other hand, when the frame synchronizing signal from the gate circuit 23 is no longer obtained, the counter 31 is not cleared and counts the pulses from the detector 29. When the count value reaches a predetermined number, for example, "8", the output signal SL of the counter 31 becomes high level. The output signal SL is supplied to the enable terminal of the counter 31, so that the counter 31 stops counting. The output signal SL is supplied to the gate circuit 23 through the OR gate 24. That is, the gate signal PW
Is always at a high level, and the gate circuit 23 is released. When the pulse from the frame sync signal detection circuit 22 is obtained from the gate circuit 23, the counter 31 is cleared, the signal output SL falls to the low level, and the counter 31 returns to the countable state.

That is, when the phase of the output carry pulse SFC of the counter 26 is largely deviated from the frame sync signal in the reproduction signal, and the detection signal of the frame sync signal is not included in the window pulse PW, this is detected by the monitoring counter 31. The counter 26 is detected and forcibly cleared so that the phase of the output carry pulse SFC of the counter 26 coincides with the position of the frame synchronization signal of the reproduction signal.

The operation of the circuit of FIG. 1 will be further described with reference to a time chart as in the case of the above-mentioned conventional example.

FIG. 2 corresponds to FIG. 6 and shows an operation example when a period shorter than one frame period occurs due to cycle slip and when dropout occurs. A in the figure is the output SFO of the frame synchronization signal detection circuit 22, B in the figure is the output PW of the OR gate 24, C in the figure is the output SFW of the gate circuit 23, and D in the figure is the output of the counter 26. This is the carry pulse SFC, and E in the figure is the output SFG of the OR gate 25.

As is clear from this figure, when a cycle slip that is shorter than the frame period occurs, the width of the window pulse becomes shorter as shown in FIG.
If it is within -3 bits with respect to the normal frame sync signal position, a detection pulse will be obtained from the gate circuit 23. That is, since the cycle slip is at most ± 3 bits, the detection signal of the frame synchronization signal is obtained from the gate circuit 23.

Since the counter 26 is cleared by the pulse at this time before the carry pulse SFC is generated, the output carry pulse S of the counter 26 is outputted.
FC goes out during the period in which this cycle slip occurs as shown in FIG.

On the other hand, when the dropout occurs, the frame sync signal does not appear in the output of the gate circuit 23 because the frame sync signal does not exist within the window pulse width of the gate signal PW. However, since the counter 26 is correctly cleared by the detection signal of the frame synchronization signal before the dropout occurs, the output carry pulse SFC of the counter 26 becomes a signal of the correct frame period, and this is taken out as the signal SFG through the OR gate.

FIG. 3 similarly shows a case where a cycle slip and a dropout occur, and in this example, the cycle slip causes a period longer than the frame period. In this case, since the counter 26 is cleared by the signal SFW obtained from the gate circuit 23 after the carry pulse SFC is generated, the length of the period after the cycle slip is different from the normal one. .. However, the output of the OR gate 25 is as shown in FIG.

FIG. 4 shows the case where the pseudo sync pulse is mixed and the case where the frame sync signal is lost for a long period of time by setting the reproducing device in the search mode. In this case, since the pseudo sync pulse rarely falls within the window pulse width, the gate circuit 23 obtains the detection signal of the frame sync signal in a state where the pseudo sync pulse is removed.

On the other hand, during the search mode period in which the frame synchronization signal detection circuit 22 cannot obtain the frame synchronization signal, when the counter 31 for monitoring detects that there is no frame synchronization signal for eight frame periods, this counter 31 When the gate circuit 23 is gated from the gate circuit 23 by the output signal SL of FIG. 4 (FIG. 4F), the gate circuit 23 is opened and the normal mode is entered after the search mode. 31 is cleared and the counter 26 is cleared. Therefore, the output pulse S of the counter 26
FC becomes slightly discontinuous at the time point after the search mode as shown in FIG. 7D, but thereafter, a signal of a correct frame period can be obtained.

As described above, according to the present invention, a compensation circuit for a frame synchronization signal can be realized with a simple structure without using a memory having a large capacity as in the prior art.

Further, since the detection signal of the frame synchronization signal is gated by the gate pulse having the window width which is expected for the time length in which the cycle slip occurs, an erroneous pulse is generated at the same position in each frame period. Even if it is obtained from the detection circuit, there is an effect that the erroneous pulse can be removed.

The present invention is not limited to the case of a reproducing apparatus for a digital PCM audio disc, but can be used as a compensating circuit for detecting a block sync signal or the like even when recording a digital signal in baseband. is there.

[0057]

As described above, according to the present invention, the sync signal is detected from the reproduced digital signal, and the pulse generation circuit is cleared by the output signal obtained by gating the detection signal of the sync signal. To generate a pulse, form a window pulse having a pulse width of some period portion before and after the timing of one block period counted by the pulse generation circuit, and supply this window pulse to the gate circuit. Then, the pulse width section, the gate circuit is opened, the signal of the block period obtained based on the output signal of the pulse generation circuit is counted as a clock, and when the count value is equal to or more than a preset value, The gate circuit is forcibly released, and the output signal of the gate circuit and the output signal of the pulse generation circuit are reproduced as synchronization signals. Therefore, a compensation circuit for the frame synchronization signal can be realized with a simple configuration without using a large-capacity memory, etc., and a gate pulse with a window width that allows for the length of time during which cycle slip occurs is used for the frame synchronization signal. Since the detection output is gated, even if an erroneous pulse is obtained from the frame synchronization signal detection circuit at the same position in each frame period, the erroneous pulse can be removed.

[Brief description of drawings]

FIG. 1 is a system diagram of an example of a compensation circuit for a frame synchronization signal according to the present invention.

FIG. 2 is a time chart for the explanation.

FIG. 3 is a time chart for the explanation.

FIG. 4 is a time chart for the explanation.

FIG. 5 is a system diagram showing an example of a conventional frame synchronization signal compensation circuit.

FIG. 6 is a time chart for the explanation.

FIG. 7 is a time chart for the explanation.

FIG. 8 is a time chart for the explanation.

[Explanation of symbols]

 22 frame synchronization signal detection circuit 23 gate circuit 24, 25 OR gate 26, 31 counter 28, 29 detector 30 flip-flop circuit

Claims (1)

[Claims] 1. A bit pattern which is modulated by a run-length limited code and is divided into blocks for each unit of time, and a bit pattern which does not appear in the normal modulation of the run-length limited code is added to the data in block units as a synchronization signal. An apparatus for reproducing a digital signal in a reproduced state, the detection circuit detecting the synchronization signal from the reproduced digital signal, the gate circuit for gated the detection signal of the synchronization signal from the detection circuit, While being cleared by the output signal of the gate circuit,
A pulse generating circuit for counting the period of one block to generate a pulse, and forming a window pulse having a pulse width of a slight period part before and after the timing of the period of one block counted by the pulse generating circuit, This window pulse is supplied to the gate circuit to be cleared by the window pulse forming circuit that opens the gate circuit in the pulse width section and the output signal of the gate circuit, and the output signal of the pulse generating circuit. A block cycle signal obtained on the basis of a clock, and a monitoring circuit for forcibly releasing the gate circuit when the count value exceeds a preset value. Is reproduced as a synchronizing signal. Reproducing apparatus of the barrel signals.