JPH0146938B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit used in PCM playback equipment, such as a PCM audio disc player.

In a PCM audio disk player, an analog signal is sampled at regular intervals, converted to a digital signal by an A/D converter, and a synchronization signal is added at each sampling period and recorded on a PCM audio disk. The analog signal at the time of recording is reproduced based on the digital code read from this disk.
FIG. 1 shows the digital code pattern read out from the PCM audio disk during playback. During playback, synchronization signals S ₁ , S ₂ . . . are detected from the continuous digital code pattern A, and the synchronization signals S ₁ ,
Together with S _{2 .} . . , the delimiter of each data D ₁ , D _{2 .} . . is detected and the data D ₁ , D ₂ .

Here, the synchronization signal S is composed of a specific digital pattern, and this digital pattern is detected by the synchronization circuit, but in reality, the digital pattern of the synchronization signal may be lost due to dust on the disk, or The same pattern as the synchronization signal may occur in the data signal and may be mistaken for a synchronization signal. Therefore, the actual synchronous circuit has the configuration shown in FIG. In Figure 2, 1 is a data input terminal, 2 is a clock input terminal, 3 is a shift register, 4 is an N-ary counter, 5 is an M-ary counter, and 6
is a synchronous output terminal. FIG. 3 is a time chart of the synchronous circuit shown in FIG. The operation of the synchronous circuit will be explained below with reference to FIG.

A digital signal from an input terminal 1 is written bit by bit into a shift register 3 by a clock from an input terminal 2 synchronized with this digital signal. Here, when a specific digital signal pattern (for example, "11000101") indicating a synchronization signal is written to the shift register 3, the shift register 3
A signal indicating that a synchronizing signal pattern has been detected is obtained at the output of the AND gate 3a. This is pattern output 1 on the time chart shown in Figure 3.
It is 0. The clock is also supplied to an N-ary counter 4 and an M-ary counter 5. Here, the values of N and M are set such that N is small and M is large relative to the value P which is the sum of the clock numbers of one block B, that is, the synchronization signal S and data signal D shown in FIG. The gate 4a of the N-ary counter 4 is opened before the synchronizing signal pattern is output, and when the synchronizing signal pattern is received, it is output as a synchronizing output. However, in the pattern output 10 of FIG. 3, when the synchronizing signal pattern is lost as shown by the dotted line 10a, after the gate 4a of the N-ary counter 4 is opened, the M-ary The output of the counter 5 is output via the gate 5a as a supplement to the synchronizing signal. When the synchronization signal is output from the gate 5a, the N- and M-ary counters 4 and 5 are reset. This is the third
N to M for the synchronization signal pattern as shown in the figure.
A clock interval window is opened, and if a synchronizing signal pattern comes in this interval, it will be output as synchronizing signals 13a, 13b, and 13c. If the synchronizing signal pattern 10a is lost due to scratches or dust, the synchronizing signal 13m will be output at the last M clock. It works to replenish and prevent synchronization disturbances.

However, the conventional technology has the following problems. That is, when the digital signal is lost for a long period of time (multiple blocks) due to large dust or scratches, the synchronization pattern detection composed of the N-ary counter 4 and the M-ary counter 5 is used for each replenishment. Since the position of the window shifts, when the correct synchronization pattern arrives after replenishment multiple times, the window position shifts so much that the synchronization signal cannot be detected and the recovery of the synchronization signal is delayed. FIG. 4 shows this situation using a time chart. In FIG. 4, 14 is a pattern output, 15 is an open period of a synchronization pattern detection window, and 16 is a synchronization output. As shown by the dotted line in the pattern output 14, the synchronization signal pattern 14
When a and 14b are lost, the terminals 15a and 15b of the gate 5a of the M-ary counter 5 output supplemented synchronization signals 16a and 16b. However, the fourth synchronization pattern 14 ₂ was output at the correct position, but
Since the position of the window 15 has shifted, the supplemented synchronizing signal 16c is output again, and the synchronizing signal cannot be output at the correct position until the synchronizing signal pattern comes to the position of the window 15 again. In other words, it is slow to recover the normal synchronization signal output.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit which eliminates the above-mentioned drawbacks of the prior art, recovers synchronization signals more quickly, and reproduces data signals correctly.

In the present invention, when replenishing the synchronization signal when the synchronization signal pattern is continuously lost, the frequency division ratio of at least one counter is changed, and the position of the window for determining the synchronization signal pattern set by the two counters is changed. This ensures that the synchronization signal does not deviate from the synchronization signal.

The present invention will be explained in detail below with reference to FIGS. 5 to 7. FIG. 5 is a block diagram of an embodiment of the present invention, in which the same symbols as in FIG. 2 have the same functions, 21 is an M'-ary counter, 22 is a set,
A flip-flop with a reset terminal, 23 is a set input. This is the same as the conventional example in that the shift register 3 detects a synchronizing signal pattern, and if there is an output from the shift register 3 within the period of the gate 4a opened in advance by the N-ary counter 4, it is regarded as a synchronizing signal. The M'-ary counter 21, which generates a complementary synchronizing signal when the synchronizing signal pattern is lost due to scratches, dust, etc., is a counter that can be switched to an M-ary counter or a P-ary counter depending on the level of the set input 23. When a regular synchronizing signal is detected from the synchronizing signal pattern, the flip-flop 22 is in the set state, and the frequency division ratio of the M'-adic counter 21 is M. When the synchronizing signal pattern disappears and the M'-ary counter 21 operates to replenish the synchronizing signal once, the flip-flop 22 enters the reset state, and the output Q of the flip-flop 22 changes the division ratio of the M'-adic counter 21 to P. Switch. Here, P is the same value as the number of clocks in one block length. If data is lost for a long period of time and the synchronization signal is replenished multiple times, it is replenished at the clock number M at first;
After that, replenishment is performed at the clock number P, so the position of the window for determining the synchronization signal pattern provided by the two counters (M-ary counter 4 and P-ary counter 21) does not shift, and after data recovery It becomes possible to immediately output a synchronization signal and reproduce data correctly. FIG. 6 is a time chart showing this situation. In FIG. 6, 25 is a pattern output, 26 is an N-ary counter gate, 27 is an M' counter output, and 28 is a synchronous output.

FIG. 7 is a block diagram of another embodiment of the invention. In FIG. 7, the same reference numerals as in FIGS. 2 and 5 have the same functions; 30, 31, 32, and 33 are monostable multiplexers, and 34 is a multiplexer for switching two inputs. In the embodiment shown in FIG. 7, since the N-ary counter 4 and the M'-ary counter 21 in FIG. 5 determine the window time for determining the synchronization signal pattern, this operation is replaced with a monostable multi. It is something that In FIG. 7, the monostable multi 30 has the same function as the N-ary counter 4 in FIG. 5, and inhibits the AND gate output of the shift register 3 for a period corresponding to N clock periods. Furthermore, the monostable multipliers 31 and 32 each have a pulse width corresponding to the M and P division periods of the M'-adic counter shown in FIG. It becomes the input of multi 33. The monostable multi 33 has a pulse width of one clock width, and when the synchronization signal cannot be detected, the monostable multi 31, 32
is not reset and the clock number P or M is determined by either output selected by multiplexer 34.
A synchronization signal for replenishment is output to the position corresponding to .
As explained above, in the embodiment of FIG. 7, the counter in the embodiment of FIG. 5 is replaced with a monostable multi-counter.

According to the present invention, when digital data is lost for a long period of time due to large scratches, dust, etc., the synchronization signal can be recovered quickly and is extremely effective in reproducing correct data.

[Brief explanation of drawings]

Figure 1 is an example of a digital signal pattern, Figure 2 is a block diagram of a conventional synchronous circuit, Figures 3 and 4 are time charts of a conventional synchronous circuit, and Figure 5 is a diagram of a conventional synchronous circuit.
This figure is a block diagram of one embodiment of the synchronous circuit according to the present invention, FIG. 6 is a time chart of the synchronous circuit of FIG. 5, and FIG. 7 is a block diagram of another embodiment of the present invention. 3: Shift register, 4: N-ary counter, 2
1: M′-adic counter, 22: Flip-flop,
23: Set input, 30-33: Monostable multi,
34: Multiplexer.

Claims (1)

[Scope of Claims] 1. A synchronization signal arranged at regular time intervals in continuous digital data is detected, and when the synchronization signal is lost, it is supplemented and the synchronization signal is output. a synchronization circuit comprising: pattern detection means for detecting a pattern of the synchronization signal; and a gate circuit provided at the output of the pattern detection means; a first means for deriving a synchronizing signal when the output of the pattern detecting means is derived after the gate is opened; and a second means having a longer time than the first time of the first means; When the output of the pattern detecting means is not derived after the gate of the first means is opened, the gate circuit of the second means is closed.
a second means for deriving a replenishment synchronization signal at a time; and a third time when the output of the pattern detection means is not derived after the second means derives a replenishment synchronization signal at the second time. and third means for deriving a supplementary synchronization signal at the synchronization circuit. 2. A synchronous circuit according to claim 1, wherein the length of the third time of the third means is the time period. 3. In claim 1 or 2, after the third means derives the third supplementary signal, when the output of the pattern detecting means is not derived, the third means detects the third supplementary signal. A synchronous circuit characterized in that it derives a replenishment signal at a time of .