JPS6314430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a data recording/reproducing apparatus such as a video tape recorder using a rotating head type magnetic recording/reproducing apparatus, in which the mechanical precision of the heads is delicate when the heads are switched one after another to reproduce data. The present invention relates to a data recording and reproducing device that eliminates the effects of skew distortion caused by differences in tape tension.

In order to record a continuous signal on a magnetic tape using a helical scan two-head recorder and reproduce it without losing the continuity of the original signal, one of the two magnetic heads must be connected to the magnetic tape. The other magnetic head must come into contact with the magnetic tape at the same time as it leaves the magnetic tape, but this condition cannot generally be met depending on the mechanical precision of the head, the degree of elongation of the magnetic tape during recording and playback, etc. Can not. This creates a time period in which two magnetic heads are in contact with the tape at the same time, and when the same signal is recorded on both magnetic heads, during playback, this overlapping recording portion causes the playback signals from the two magnetic heads to lose continuity. Measures are taken to connect them so that they do not bend.

When signals recorded simultaneously using two magnetic heads are reproduced by heads of the same structure, the simultaneity of the reproduced output signals reproduced from the two heads depends on factors such as the elongation of the mechanical precision magnetic tape in the heads. It is normal for the signal to be lost, but it is possible to connect the signals reproduced from the two heads and obtain the same signal as the recorded signal without losing the continuity of the signal in this part. It requires quite difficult technology. The present invention relates to a data recording/reproducing device that realizes this signal connection.

PCM using conventional rotating head type magnetic recording device
Data recording and reproducing devices such as recording devices that demodulate the reproduced signal for each head and switch the demodulated signals require special and very strict conditions regarding the time difference or skew in head switching. In other words, regarding the overlapping parts of the reproduced signals when switching heads, the reproduced signal from the preceding head must be temporally earlier than the reproduced signal from the succeeding head (if the skew distortion standard is 0 to + μS) was necessary. However, when we consider playing back tapes recorded with other devices, we find that due to subtle differences in the mechanical precision of the heads, differences in tape tension, etc., tapes recorded with any device can be played back in a state that satisfies the above conditions. It was very difficult to do so, and there was a serious problem with tape compatibility. A method has also been used in which data signals are not recorded in areas where the head requires switching, but this method cannot increase the recording density of the tape.

The purpose of the invention is to solve the aforementioned problems.

Hereinafter, the present invention will be described in detail with reference to embodiments and drawings.

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and shows the case where it is implemented in a helical scan two-head type video tape recorder. Second
This figure is a waveform diagram for explaining the operation of FIG. 1.

In FIG. 1, reference numeral 1 denotes a rotating drum equipped with a head for reproducing a tape on which an FM modulated signal to be reproduced is recorded, using a helical scan method; 2 and 3 denote magnetic heads attached to the rotary drum 1; 4 and 5 are FM demodulators, 6 and 7 are sync separation circuits that separate the sync signal and demodulation signal from the demodulation signal, 8 and 9 are memories that temporarily store the sync-separated data signal, and 10 is a memory after reading out the memory. a switching circuit for switching data signals; 11 and 12 are tone wheels for indicating switching positions of the magnetic heads 2 and 3; 13 is for generating a write memory selection signal from the signals from the tone wheels 11 and 12 and the synchronization signal; Write-side memory selection signal generation circuits 14 and 15 that control memory writing of data signals are arranged to select the memory 8,
9 is a memory write control circuit that generates a write signal to 9; 16 is a write side memory selection signal generation circuit 13;
a read-side memory selection signal generation circuit that generates a read memory selection signal based on the signal from the memory 8 and the signal indicating the memory content from the memories 8 and 9, and controls the reading of data signals from the memories 8 and 9; , 17 and 18 are memory read circuits that generate memory read clock signals for reading signals from the memories 8 and 9 based on the signal from the read side memory selection signal generation circuit 16 and the signal indicating the memory content capacity. This is a control circuit.

In FIG. 2, a and b are waveforms of FM signals which are reproduced signals from magnetic heads 2 and 3, c and d are demodulated signal waveforms obtained by demodulating reproduced signals a and b by FM demodulators 4 and 5, e, g is a data signal waveform separated from demodulated signals c and d, f and h are demodulated signals c and d
The more separated synchronization signal waveforms, i and j are tonewheel signal waveforms, and the period j ₁ −i ₁ = i ₂ − _{j 1} = j ₂ − _{i 2}
=... is the effective time of the magnetic heads 2 and 3, and i ₁ ~
Up to j ₁ , the reproduction signal a from the magnetic head 2 is a valid signal, and from j ₁ to i ₂ , the reproduction signal b from the magnetic head 3 is a valid signal. Memory selection signal waveform to control, l, m
is the signal waveform that serves as the reference clock for writing to the memory, n and p are the signal waveforms that indicate the memory contents of memories 8 and 9, q is the read memory selection signal waveform that controls reading from the memory, and r and s are the memory Signal waveforms, t, u that serve as the reference for the read clock signal
is the output signal waveform from the memory, and v is the composite signal waveform. Regarding the data signals e and g, e ₁
and g ₁ , e ₂ and g ₂ , e ₃ and g ₃ , e ₄ and g ₄ , and e ₅ and g ₅ are each the same data signal.

Next, the operation of this device will be explained with reference to FIGS. 1 and 2. First, during reproduction, the reproduction output waveforms of the magnetic heads 2 and 3 are intermittent as shown in Figure 2 a and b.
This is an FM signal, which is sent to the FM demodulator 4 for each head.
5, demodulated signal waveforms as shown in FIG. 2c and d are obtained. In this waveform, the upper part is a data signal, and the lower part is a synchronization signal indicating the timing of the data signal. The demodulated signal is separated into a data signal and a synchronization signal by synchronization separation circuits 6 and 7.
The signals are separated into systems, and data signals have waveforms as shown in FIG. 2e and g, and synchronization signals have waveforms as shown in FIG. 2f and h.

On the other hand, when switching the signals from the magnetic heads 2 and 3 to make a continuous signal, first, the tone wheel signals i and j from the tone wheels 11 and 12 for detecting the switching position of the magnetic heads and the synchronization separation circuits 6 and 7 are used. A write memory selection signal k is generated from the separated synchronization signals f and h. This write memory selection signal k is generated approximately in the middle of the overlapping portion of the reproduction signals a and b from each magnetic head 2 and 3, and at the same time as the synchronization signal from the preceding magnetic head 2 (the synchronization signal f in FIG. 2). This is done, for example, by counting the synchronization signal f and a clock signal (not shown) so that they occur in the middle. This write memory selection signal k is sent to memory write control circuits 14 and 15. In FIG. 2, the write memory selection signal k is represented by a change of "0" and "1". The memory write control circuits 14 and 15 generate a write control signal to the memory based on the write memory selection signal k and the synchronization signals f and h, but first, the preceding magnetic head 2 generates a clock signal based on the signal l. Writing to the memory 8 is performed by the synchronous signal f, and writing to the memory 8 is inhibited when the first pulse of the synchronizing signal f appears after the write memory selection signal k changes. On the other hand, on the succeeding magnetic head 3 side, writing to the memory 9 is started by a clock signal based on the signal m from the time when the first pulse of the synchronizing signal h appears after the write memory selection signal k changes.

In Figure 2, e ₁ and g ₁ , e ₂ and g ₂ , e ₃ and g ₃ , e ₄
, g ₄ , e ₅ , and g ₅ are the same signal, and e ₁ , e ₂ , and e ₃ are written to the memory 8, and e ₄ and e ₅ are not written to the memory 8. On the other hand, g ₄ , g ₅ ... are written to memory 9,
g ₁ , g ₂ , and g ₃ are not written to the memory 9. By doing this, if the output signal of the succeeding magnetic head 3 side is within the lead or lag range of half the synchronization of the synchronization signal with respect to the output signal of the preceding magnetic head side, the data signal e or g is The data is written to either memory 8 or 9 without duplication or omission. Figure 2 shows a case where the output from the preceding magnetic head always lags behind the output from the succeeding magnetic head by the synchronizing pulse width, but even if this time relationship is reversed, the output to memories 8 and 9 is Data signal writing is performed in the same manner as described above.

Further, reading of the data signal t or u from the memories 8 and 9 is performed using the read memory selection signal q generated by the memory read memory selection signal generation circuit 16.
and signals n and p indicating the contents of the memories 8 and 9. Signals n and p indicating the content capacity are signals for determining the presence or absence of data signals that have not yet been read out in the memories 8 and 9. After the write memory selection signal k changes, the read memory selection signal q indicates that the signal indicating the content capacity of the memory on the preceding magnetic head 2 side (n out of n and p in FIG. 2) is empty for the first time. It changes when it appears. This read memory selection signal q is sent to the memory read control circuit 1.
7 and 18, and generate signals r and s that serve as references for memory read clock signals. Of the memory read control circuits 17 and 18, the circuit on the magnetic head side (the side that generates the read clock signal r in FIG. 2) immediately stops reading from the memory 8 when the read memory selection signal q changes. .
On the other hand, in the circuit on the succeeding magnetic head side (the side that generates the read clock signal s in FIG. 2), after the read memory selection signal q changes, the signal p indicating the memory content is sent to the memory 9 as a data signal. "Yes"
If the state is shown, reading from the beginning of the memory 9 is started immediately, and if the state is "empty", reading of the data signal from the memory 9 is started after waiting until the state is "present". do. The switching circuit 10 switches the data signals t and u read from the memories 8 and 9 using the read memory selection signal q, and generates one system of composite data signal v.

By using this method, reading from one memory is started after all of one memory has been read,
In addition, since there is no double writing of data to the memory or data loss, there is no data loss or temporal shift in the data signal in the composite data signal after reading from the memory.

As explained above, according to the present invention, the demodulated output from each magnetic head is written to the memory of each magnetic head, so that even if skew distortion occurs during playback, it is within ±1/2 of the period of the synchronizing signal. (Generally, the period of the synchronization signal is longer than the skew distortion.) This effect can be completely removed, the magnetic recording device does not require strict conditions, and the recording density of the tape can be increased. . Further, the memory used in this method only needs to be prepared for the maximum value of skew distortion, and the memory capacity can be small.

In the first embodiment, the explanation is for the case where there are two heads, but even when three or more heads are used, a demodulator, a synchronization separation circuit, a memory, a write control circuit, and a circuit corresponding to each head are provided. This can be applied by providing a read control circuit. Also, a synchronization signal pulse with a different polarity from the data signal is used as the signal switching timing, but any signal can be used as long as it can be separated from the reproduced data and inserted into the data at an appropriate cycle. But it can be used.

Next, regarding the second embodiment, considering that the reproduction signals that are reproduced simultaneously are from at most two heads, when three or more heads are used, the signals from each of the heads that are cyclically switched are A reproduction signal switching circuit that alternately switches the reproduction signal and outputs it from two output terminals is provided, and by demodulating the reproduction signal from the two output terminals, a demodulator, a synchronous separation circuit, a memory, a write control circuit, and a readout circuit are installed. A data recording and reproducing apparatus that requires only two control circuits without requiring circuits corresponding to each head will be described. Figure 3 shows the second embodiment of the present invention.
FIG. 3 is a block diagram for explaining an embodiment of the present invention, and shows a case where there are three magnetic heads. FIG. 4 shows a waveform diagram for explaining the operation. 31 is a rotating drum for cyclically rotating the head;
Reference numerals 2, 33, and 34 denote magnetic heads attached to the rotating drum 31, and the magnetic heads 2, 33, and 34 cyclically contact the recording medium for a predetermined period of time.
The recording medium is contacted in the order of →33→34→32→... 35, 36 are FM demodulators, 37, 38, 39
Reference numeral 40 indicates a tone wheel for indicating switching positions of the magnetic heads 32, 33, and 34, and 40 indicates a synchronization separation (not shown) provided corresponding to the tone wheel signals from the tone wheels 37, 38, and 39 and the demodulators 35 and 36. A write-side memory selection signal generation circuit generates a write memory selection signal from a synchronization signal from the circuit and controls memory writing of data signals, 41 is a reproduction signal switching circuit, 411 is an OR circuit, 412 and 413 are first Gate circuits 414 and 415 guide the reproduction signal from the second magnetic head 33; 416 and 417 the third magnetic head 34;
A gate circuit 418 guides the reproduced signal from the
The tone wheel signal is input from the OR circuit 411 and the gate circuits 412, 414, 416 are connected to the gate circuit 412→
The gate drive signals for opening the gates in the order of 416→414→412→... are sent to the gate circuits 412, 41.
4 or 416, and 419
inputs the tone wheel signal from the OR circuit 411 and outputs the gate circuits 413, 415, 417.
In order to open the gates in the order of 15→413→417→..., the gate drive signal is applied to the gate circuits 413, 415.
Or it is a logic circuit that sequentially outputs data to 417. Other circuits not shown are similar to those shown in FIG. The gate drive signal output from the logic circuits 418 and 419 to one gate circuit has a period six times the tone wheel signal period, is in the 'ON' state for two periods of the tone wheel signal period, and is in the same logic circuit. Each of the gate drive signals output from 418 or 419 has a phase difference of two periods of the tone wheel signal, and the gate drive signal to the gate circuit 412, the gate drive signal to the gate circuit 415, and the gate drive signal to the gate circuit 414 are different from each other. Drive signal and gate drive signal to gate circuit 417, gate circuit 4
The gate drive signal to the gate circuit 16 and the gate drive signal to the gate circuit 413 each have a phase difference of one period of the tone wheel signal.

Reproduction signal reproduced by first magnetic head 32
A ₁ (see FIG. 4) is input to the first demodulator 35 by the gate signal Da in the gate circuit 412, and the reproduced signal B ₁ reproduced by the second magnetic head 33 is input to the gate circuit 415 by the gate signal Eb. The reproduced signal _C1 inputted to the second demodulator 36 and reproduced by the third magnetic head 34 is inputted to the first demodulator 35 by the gate signal Dc in the gate circuit 416, and is inputted to the first demodulator 35 by the first magnetic head 32. The reproduced signal A ₂ is input to the second demodulator 36 by a gate signal Ea in a gate circuit 413, and the reproduced signal B ₂ reproduced by the second magnetic head 33 is input to the second demodulator 36 by a gate signal Db in a gate circuit 414. The reproduced signal _C2 input to the first demodulator and reproduced by the third magnetic head 34 is input to the second demodulator by the gate signal Ec in the gate circuit 417, and the same process is repeated. In this way, 3
The reproduced signals from the magnetic heads 32, 33, 34 are alternately input to first and second demodulators 35, 36. Therefore, the inputs of the first and second demodulators 35 and 36 become Fd and Fe, respectively.

The operations after the demodulators 35 and 36 are the same as in the first embodiment.

Although the above explanation has been given for the case where the number of heads is 3, the same processing is possible when the number of heads is a parsimonious number of 5 or more, and the number of circuits adjacent to the demodulator does not need to be the same as the number of heads, but only two circuits are required. It only takes a minute.

Next, as a third embodiment, when the number of magnetic heads is an even number of 4 or more, a reproduction signal switching circuit that alternately switches the reproduction signal from each cyclically switched head and outputs it from two output terminals. By providing this, each circuit below the demodulator can be configured with two circuits. FIG. 5 is a block diagram for explaining a third embodiment of the present invention.
The case where there are four magnetic heads is shown. FIG. 6 shows a waveform diagram for explaining the operation. 51 is a rotating drum equipped with a head for cyclically contacting the recording medium; 52, 53, 54;
55 is a magnetic head attached to the rotating drum 51, which rotates cyclically, for example, from 52 to 53 to contact the recording medium for a predetermined time.
The playback switching operation is performed in the order of 54→55→.... 5
6, 57 are FM demodulators, 58, 59, 60, 61
is a tone wheel for indicating switching positions of the magnetic heads 52, 53, 54, 55; 62 is a reproduction signal switching circuit; 621 is an OR circuit;
The reproduced signals from the magnetic heads 52 and 54 are guided to a first demodulator 56. Reference numeral 622 denotes an OR circuit, which guides the reproduced signals from the second and fourth magnetic heads 53 and 55 to the second demodulator 57. Demodulators 56, 57
Other circuits (not shown) including the tone wheels 58, 59, 60, and 61 are the same as those shown in FIG. In FIG. 6, A, B, C, and D are reproduction signals from each magnetic head 52, 53, 54, and 55;
E, F are switched by the playback signal switching circuit 62 and input playback signals to the demodulators 56, 57;
nu is the tone wheel signal.

Adjacent magnetic heads, for example, the first magnetic head 5
2, the second magnetic head 53, and the fourth magnetic head 55 have time to reproduce simultaneously, but the first magnetic head 52 and the third magnetic head 5
4 and 4 do not have time to play at the same time, and always during the playback operation either the second or the fourth
Since two magnetic heads perform the reproducing operation, the reproducing signal A from the first magnetic head 52 and the reproducing signal C from the third magnetic head 54 are connected to the same OR circuit 6.
21 and input to the first demodulator. Similarly, reproduced signals B and C from the second and fourth magnetic heads 53 and 55 are connected to an OR circuit 622 and input to a second demodulator. By doing this, the sixth
As shown in the figure, four heads 52, 53, 54,
The reproduced signals from 55 are alternately input to first and second demodulators 56 and 57.

For even heads of 4 or more, demodulators 56,5
The operations after step 7 are the same as in the first embodiment.

Even in the case of an even number of heads of six or more, processing can be performed in the same manner as in this embodiment, and the number of circuits after the demodulator need not be equal to the number of heads, and only two circuits are required.

Although the data is processed using a baseband signal, it is not necessary to record the data in the form of FM modulation, and any modulation method suitable for the recording device may be used.

Furthermore, it can be applied not only to video tape recorders but also to general data recording and reproducing devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the first embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is for explaining the second embodiment of the present invention. 4 is a waveform diagram for explaining the operation of FIG. 3, FIG. 5 is a block diagram for explaining the third embodiment of the present invention, and FIG. 6 is a waveform diagram for explaining the operation of FIG. FIG. 3 is a waveform diagram for explaining the operation. 1, 31, 51...rotating drum, 2, 3, 32,
33, 34, 52, 53, 54, 55...magnetic head, 4, 5, 35, 36, 56, 57... modulator,
6, 7...Synchronization separation circuit, 8, 9...Memory, 10...
Switching circuit, 11, 12, 37, 38, 39, 5
8, 59, 60, 61...Tone wheel, 13,
40...Writing side memory selection signal generation circuit, 14,
15...Write control circuit, 16...Read-side memory selection signal generation circuit, 17, 18...Read control circuit, 41, 62...Reproduction signal switching circuit.

Claims (1)

[Claims] 1. A data signal is continuously transmitted by switching the plurality of heads cyclically so that two of the plurality of heads (N≧2) simultaneously contact the recording medium for a predetermined period of time. In a data recording and reproducing apparatus that performs recording and reproducing digitally, there are N demodulators corresponding to each head that demodulates a reproduced signal from the head, and each of the demodulators that separates the demodulated signal into a data signal and a synchronization signal. The separated data signals are written based on the memory write clock signal and read out based on the memory read clock signal, and a memory content display indicating the presence or absence of unread data signals. N corresponding to each of the above-mentioned synchronous separation circuits that output signals
a switching circuit that selects the data signal read out from each memory based on a read memory selection signal and converts it into a continuous signal; and a tone wheel signal from a tone wheel provided corresponding to each head. For each input of A write-side memory that cuts off output of a write memory selection signal corresponding to the preceding head in the middle of a synchronization signal of a reproduction signal from the preceding head and outputs a write memory selection signal corresponding to the succeeding head. A selection signal generation circuit inputs a write memory selection signal corresponding to a predetermined head and a synchronization signal from a synchronization separation circuit, generates the first synchronization signal after the input of the write memory selection signal, and selects the write memory. N write control circuits corresponding to each of the memories that generate the memory write clock signal that stops at the first synchronization signal after the signal input is disconnected, and each input of the write memory selection signal corresponding to each head. When the memory content display signal corresponding to the preceding write memory selection signal indicates nothing after the write memory selection signal is input, a read memory selection signal corresponding to the input write memory selection signal is outputted; a read-side memory selection signal generation circuit that cuts off the output of a read memory selection signal corresponding to the preceding write memory selection signal; a read memory selection signal corresponding to a predetermined head; and a memory content display signal from the memory; When the read memory selection signal is input and the memory content display signal indicates presence, the recorded data signal is read from the memory from the beginning, and when the read memory selection signal becomes disconnected, the data signal is read. A data recording and reproducing apparatus comprising: N read control circuits corresponding to each of the memories and outputting the memory read clock signal for terminating the data recording and reproducing apparatus. 2. Data in which a data signal is continuously recorded and reproduced by cyclically switching a plurality of heads such that two heads out of a plurality of heads (N≧3) contact the recording medium simultaneously for a predetermined period of time. In the recording and reproducing apparatus, a reproduction signal switching circuit that alternately switches reproduction signals from each of the cyclically switched heads and outputs the same from two output terminals;
two demodulators that demodulate the reproduced signal and correspond to the output end of the reproduced signal switching circuit; and two synchronizers that correspond to each demodulator and separate the demodulated signal into a data signal and a synchronization signal. a separation circuit; and each synchronous separation circuit for writing the separated data signal based on a memory write clock signal and reading it based on a memory read clock signal, and outputting a memory content display signal indicating the presence or absence of an unread data signal. two memories corresponding to the circuits, a switching circuit that selects and converts data signals read from each of the memories into continuous signals based on a read memory selection signal, and a tone wheel provided corresponding to each of the heads. Each time a tonewheel signal is input from the head, the overlapped portion of the playback signal from the previous head corresponding to the tonewheel signal input earlier and the playback signal from the succeeding head corresponding to the tonewheel signal input subsequently. and in the middle of the synchronization signal of the reproduction signal from the preceding head, the output of the write memory selection signal corresponding to the preceding head is cut off, and the output of the write memory selection signal corresponding to the succeeding head is cut off. a write-side memory selection signal generation circuit to output;
A synchronization signal from a synchronization separation circuit corresponding to a predetermined memory and a write memory selection signal are input, and this occurs at the first synchronization signal after the write memory selection signal is input, and the input of the write memory selection signal is disconnected. two write control circuits corresponding to the respective memories, which generate the memory write clock signal that stops at the first synchronization signal after the clock has passed; When the memory content display signal corresponding to the preceding write memory selection signal indicates nothing after the write memory selection signal is input, the read memory selection signal corresponding to the input write memory selection signal is outputted, and the read memory selection signal corresponding to the input write memory selection signal is outputted. a read-side memory selection signal base circuit that cuts off the output of a read memory selection signal corresponding to a preceding write memory selection signal; a memory content display signal from a predetermined memory; and a read memory selection signal corresponding to the memory; When the read memory selection signal is input and the memory content display signal indicates presence, the data signal recorded in the memory is read from the beginning until the read memory selection signal is disconnected. 2. A data recording/reproducing apparatus comprising: two read control circuits corresponding to each of the memories, each of which outputs the memory read clock signal for terminating the read.