JPH04355273A - Recording and reproducing device for digital data - Google Patents

Abstract

PURPOSE:To attain a high density recording by reducing the number of blocks constructing a postamble. CONSTITUTION:A block address W1 is detected by a block address remaining block number of the detection circuit 73. The detected block address M1 is calculated in a calculation circuit 75. This is loaded each time of detection of the block address W1 to a counter 74 and counted down with a reproducing word clock. When the 19th block is detected, the output of a comparator 77 is reset to zero, a window pulse WP is raised and therefore, the last PCM audio signal can be detected. When the 19th block cannot be detected, the window pulse WP is raised by counting down the output of the calculation. Thus, the postamble can be correctly detected and accordingly, remaining data not yet erased will not be taken even when the number of blocks of the postamble is reduced and the high density recording can be attained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording and reproducing apparatus which is suitable for use in high-definition VTRs and the like and which records digital audio signals over multiple channels in a PCM format as part of an analog video signal.

0002

2. Description of the Related Art In digital data recording and reproducing devices such as high-definition VTRs and 8mm VTRs that record digital audio signals over multiple channels as part of analog video signals using PCM, one frame of analog video signals is recorded. Recording is divided into multiple inclined tracks.

In such cases, a rotating magnetic head device as shown in FIG. 8 is often used.

As shown in FIG. 1A, in this rotary magnetic head device, rotary heads Ha to Hd are attached to a drum 84 that rotates at, for example, 3600 rpm. A magnetic tape 85 is wound diagonally around the circumferential surface of the rotating drum 84, and the magnetic tape 85 is wound at a constant speed in this state.
runs.

The rotary heads Ha and Hc are located close to each other, the rotary head Hb is disposed at an angular interval of 180° from the rotary head Ha, and the rotary head Hd is disposed at an angular interval of 180° from the rotary head Hc. Ru. The rotating heads Ha and Hc have a double azimuth configuration having two gaps with different azimuth angles, as shown in FIG. 8(b). The rotary heads Hb and Hd also have a similar configuration.

[0006] One frame of high-definition system is 1/30
seconds, the rotating drum 84 rotates 2 times in one frame period.
The magnetic tape 85 is rotated, and the pair of rotating heads (Ha and Hc pair, Hb and Hd pair) scans the magnetic tape 85 a total of four times. Therefore, like the track pattern shown in FIG.
Four segments (eight tracks) are formed in one frame on the magnetic tape 85. Analog video signals are processed in units of one frame period.

In FIG. 9, T1 to T8 are video tracks, T1 and T2, T5 and T6 are tracks formed simultaneously by rotary heads Hb and Hd, and T3 and T4, T7 and T8 are tracks formed by rotary heads Ha. and Hc simultaneously.

Each of the tracks T1 to T8 is formed by scanning a rotary head from the lower edge of the magnetic tape 85, and the area from the start end of the track to a predetermined range is defined as the audio track 86S, and from there to the end end. The area up to is designated as video track 86V.

The audio track 86S is divided into two areas. The audio track 86S of the track T3 formed by the rotary head Ha is equally divided into areas A1 and A2, and the audio track 86S of the track T3 formed by the rotary head Hc is divided equally into areas A1 and A2.
4 audio tracks 86S are equally divided into areas A3 and A4. Similarly, audio track 8 of track T5
6S is divided into areas A5 and A6, and track T6
The audio track 86S is divided into areas A7 and A8. Areas A1 to A8 of these four tracks include 1
A field's worth of four-channel digital audio signals, such as PCM audio signals, are recorded, as well as block addresses W1 (details will be described later), etc.

[0010] Digital audio signals are processed in units of one field period. More specifically, channels CH3 and CH4 are placed in areas A1, A3, A5, and A7.
Channel CH1 and CH2 system PCM audio signals, block address W1, etc. are recorded in areas A2, A4, A6, and A8.

FIG. 10 shows a data format (signal format) in one track, for example, T3.
The book track is audio track 8 including areas A1 and A2.
Consisting of 6S and video signal track 86V (see the same figure)
a)). As shown in FIG. 10(b), area A2 where the PCM audio signals of CH1 and CH2 are recorded consists of a preamble, a PCM audio signal, and a postamble, and is composed of 9 blocks, 32 blocks, and 9 blocks, respectively. There is.

One block of the preamble is shown in FIG. 10(c).
As shown in the figure, the sync block is composed of a sync block (SYNC block) and a PLL pull-in block, and the sync block has a 1-word sync code SYNC that functions as a block synchronization signal at the beginning, followed by a 1-word block. Address W1, 1 word control and I
D code W2 and one word parity code P for W1 and W2 are arranged in this order.

[0013] The PLL pull-in block is a block assigned to facilitate the synchronization pull-in of a PLL (described later) provided for generating a processing clock. data (e.g. 3
8 MHz frequency data) is repeatedly inserted for 31 words.

[0014] The postamble is 8-10 for 35 words.
Only modulated data is inserted. This is because the preamble consists of a sync block and a PLL pull-in block in order to generate a block address for the PCM audio signal, but the postamble does not have such a function, so no sync block is inserted. . The postamble is inserted for the following purposes.

[0015] The position of the area where the PCM audio signal is recorded varies due to factors such as jitter, adjustment error, and temperature characteristics. If FIG. 11(a) is a standard pattern, the tape pattern varies in the positive and negative directions as shown in FIG. 11(b) and FIG. 11(c) due to the reasons mentioned above. If a new PCM audio signal is after-recorded for such a tape pattern as shown by the broken line in the same figure, depending on the previous tape pattern, after-recording may be performed as shown in (b) in the same figure, or ( c.
) may be recorded after recording.

If the previous data (PCM audio signal) remains due to after-recording with respect to the original tape pattern having such variations, it may cause a malfunction. For this reason, the total block length of the preamble and postamble is made longer than this variation, so that the previous data is always overwritten during after-recording. Therefore, (b) and (c)
), the previous data is completely overwritten.

[0017]

[Problem to be Solved by the Invention] However, as mentioned above, if the preamble and postamble lengths are set sufficiently long in consideration of the variations in the tape, high-density recording will be hindered. It is preferable to keep the area short.

[0018] As mentioned above, the preamble is
Since the postamble is also used to draw in data, it is difficult to make it too short, but since the postamble is only used as a margin for after-recording, the previous data may be erased and remain after the after-recording. If you can deal with it without any particular problems, you can shorten the postamble.

For example, as shown in FIG. 12, the postamble is limited to about two blocks. At that time, if there are discrepancies in the tape, etc., PCM is used for after-recording.
The postamble added to the audio signal can no longer completely overwrite the previous data (as shown by diagonal lines in FIG. 11(d)).

[0020] If this problem can be completely dealt with circuit-wise,
Even if the postamble is made sufficiently short, there is no risk that unerased data will be picked up as post-recording data.

[0021] Therefore, the present invention solves this problem, and even if the number of blocks in the postamble is made shorter than the number of blocks in the preamble, there will be no malfunction caused by picking up unerased data. The present invention proposes a digital data recording and reproducing device as described above.

[0022]

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the first invention, a preamble including digital data and a plurality of sync block data added at the front stage thereof, and a preamble including a plurality of sync block data at the rear stage of the digital data. The present invention is characterized in that a postamble including added sync block data and composed of a smaller number of blocks than the above-mentioned number of blocks is simultaneously recorded.

[0023] In the second invention, when reproducing digital data to which a postamble including a plurality of sync block data is added, a detection means is provided for detecting sync block data inserted into the postamble, and The present invention is characterized in that valid data of the reproduced digital data is determined based on the detection output.

[0024]The third invention records digital data to which a preamble and a postamble are added on a part of a diagonal track, reproduces this to obtain reproduced digital data, and detects the postamble data. The present invention is characterized in that the reproduced digital data up to the last time is used as valid data.

[0025]

[Operation] The number of constituent blocks of the postamble is shorter than the number of blocks of the preamble, and in this example, it has a two-block structure as shown in FIG. Each block of the postamble has a sync block SYN like the preamble block.
It consists of blocks of C and 8-10 modulation data. Therefore, the postamble also has a block address.

When reproducing data after after-recording, the block address W1 inserted in this postamble is detected, and when the block address W1 inserted in the postamble is detected, subsequent reproduction is performed. Avoid using data.

Then, as shown in FIG. 11(d), for example, the unerased data (P
Even if a commercial audio signal (CM audio signal) exists, this data is never used as data after after-recording.

Even if a dropout occurs before the postamble, there is no problem as long as the postamble can be detected. If the postamble drops out, deal with it by other means.

[0029]

[Embodiment] Next, an example of a digital data recording/reproducing apparatus according to the present invention will be described.
The application will be described in detail with reference to the drawings.

In the present invention, as is clear from the data format shown in FIG.
A preamble and a postamble are inserted before and after the audio signal ((b) in the same figure). While the PCM audio signal is composed of 39 blocks, the preamble is composed of 9 blocks, and the postamble is composed of 2 blocks as described later, for a total of 5 blocks.
There are 0 blocks.

The PCM audio signal is composed of a 4-word sync block SYNC and 31 words of PCM data, as shown in FIG. 2(c). sync block SYNC
has the same data structure as the preamble, so its explanation will be omitted.

The preamble is composed of nine blocks as described above, and each block is composed of a 31-word PLL pull-in block composed of a 4-word sync block SYNC and 8-10 modulation data, as shown in FIG. Become. Therefore, its configuration is the same as that in FIG.

The number of blocks constituting the postamble is shorter than the number of blocks constituting the preamble, and in this example, it consists of two blocks. That is, as shown in FIG. 3(e), each block is composed of a 4-word sync block SYNC and a 31-word block, similar to the block contents of the preamble, and the subsequent blocks use 8-10 modulation data. As shown in the figure, the sync block SYNC includes a sync code, a block address W1, a control and ID code W2, and a parity P of these codes W1 and W2.
It is made up of.

[0034] When recording and reproducing a PCM audio signal that includes a postamble with a small number of constituent blocks and in which the block address W1 is inserted, the block address W1 of the postamble is detected especially during reproduction. This controls the writing of PCM audio signals into the memory. This is because the break in the PCM audio signal can be detected by the block address W1.

For example, as shown in FIG. 2(a), after-recording is performed on the original track T1 and a new track T1 is created.
Let us consider a case in which data from the 48th block of the original track T1 remains after after-recording due to variations in the timing at the start of head scanning.

Even in such a case, by detecting the block address W1 of the 49th block (49') or the 50th block (50') after after-recording, the last data block of the PCM audio signal after after-recording can be detected. (48th block (48th block)
′)) can be recognized correctly.

Therefore, after the 48th block is stored in memory, there is no possibility that the data of block 48 written on the original track T1 will be mistakenly recognized as data after recording and written into the memory.

Even if there is a dropout before the postamble as shown in FIGS. 2(b) and 2(c), the block address W1 of the postamble can be detected, so malfunctions will not occur in this case as well.

When a dropout occurs in the postamble itself, the position of the postamble is predicted by a signal counted based on the block address W1 detected in the PCM audio signal, and the position of the postamble is predicted by the predicted window pulse WP. The end of the signal is recognized.

From the above, by inserting the block address W1 into the postamble, the position of the postamble can be detected accurately, so even if the number of inserted blocks is reduced, there will be no unerased blocks. Malfunctions such as picking up data do not occur. Therefore, the number of blocks in the postamble is smaller than that in the preamble.

Next, an example of recording and reproducing digital data formatted in this manner will be described below.

FIG. 3 is a system diagram showing an example of a high-definition VTR, in which numeral 1 denotes a video signal processing circuit, which processes a high-definition video signal from an input terminal 2 and converts it into a recording signal. A signal reproduced from the magnetic tape 85 is processed by the video signal processing circuit 1 and taken out to the output terminal 3. In the video signal processing circuit 1, the luminance signal Y is time-axis expanded, and the two color difference signals PR and PB are line-sequentialized and then time-axis compressed. Thereafter, the luminance signal and line-sequential color difference signal are time-division multiplexed. All of these multiplexing processes are digital processes.

[0043] The multiplexed signal converted back to an analog signal is subjected to FM modulation to produce a recorded video signal. During playback, the luminance signal and color difference signal are demodulated by signal processing reverse to that during recording.

Two channels of recorded video signals from the video signal processing circuit 1 are supplied to video side terminals V of video/audio switching switches S1 and S2.

Recording amplifier 4 is connected to the output terminal of switch S1.
a, 4b are connected, and recording amplifiers 4c, 4d are connected to the output terminal of the switch S2. The output signal of the recording amplifier 4a is connected to the recording side terminal r of the recording/playback switching switch.
is supplied to the rotary head Ha via. Similarly, the output signals of the recording amplifiers 4b, 4c, 4d are transmitted to the rotary heads Hb, H via the recording side terminal r of the recording/reproduction switch.
c and Hd, respectively. Rotating head Ha~Hd
As a result, the recording video signal is recorded in the video signal area 86S of the diagonal track as shown in FIG.

From the magnetic tape 85, the rotating heads Ha to Hd
The reproduced video signals are supplied to the reproduction amplifiers 5a to 5d through the reproduction side terminal p of the recording/reproduction changeover switch, respectively. The output signal of the reproduction amplifier 5a and the output signal of the reproduction amplifier 5b are connected to a head switching switch S.
3 input terminals a and b, respectively. The switch S3 is controlled by a switching pulse whose phase is synchronized with the rotational phase of the rotary heads Ha to Hd, and
Select the output signal of the rotating head that is scanning 5. Similarly, the output signals of the reproducing amplifier 5c and the reproducing amplifier 5d are alternately selected by the switch S4. switch S3
The reproduced signals from S4 and S4 are supplied to the video signal processing circuit 1.

11, 12, 13, 14 are the first to fourth
input terminals 21, 22, 23, to which analog audio signals of the channels (CH1 to CH4) are respectively supplied;
24 is an A/D converter that converts the audio signal of each channel into a digital signal, and 6 is a memory that stores the digital audio signal. The memory 6 can store, for example, two fields of PCM audio signals. A correction code is added to the A/D converted data by an error correction circuit 18.

The audio signal read from the memory 6 and the added correction code are supplied to input terminals 9 of audio recording processing circuits 7a and 7b, respectively. Output terminal 1 of each audio recording processing circuit 7a, 7b
The recording audio signal (PCM audio signal) taken out at 0 is supplied to the recording amplifiers 4a to 4d through the audio side input terminals S of the switches S1 and S2. Then, the data is recorded on the magnetic tape 85 by the rotary heads Ha to Hd via the recording/reproduction changeover switches S1 and S2. The audio recording processing circuits 7a and 7b will be described later.

The magnetic tape 8 is rotated by the rotating heads Ha to Hd.
The PCM audio signals reproduced from 5 are supplied to input terminals 15 of audio reproduction processing circuits 8a and 8b via recording/reproduction changeover switches S3 and S4, respectively. Although the audio reproduction processing circuits 8a and 8b will be described later, a reproduced audio signal is output to their output terminals 16, and a reproduction address is output to their output terminal 17. According to the playback address, the playback audio signal is stored in the memory 6.
will be written to.

The audio recording processing circuits 7a and 7b have control and I/O signals formed from information from the system controller.
The D code W2 is supplied and recorded on the magnetic tape 85 together with the PCM audio signal. The reproduced control code is supplied from the audio reproduction processing circuits 8a and 8b to the system controller. Error detection and correction of the reproduced PCM audio signal is performed by the error correction circuit 18. The four-channel PCM audio signals read from the memory 6 are converted into analog signals by the D/A converters 31-34 and taken out to the output terminals 41-44.

FIG. 4 shows the audio recording processing circuit 7a (7b).
(same as above) is shown below. The audio recording processing circuit 7a includes a block address W1, a control and ID code W2
A W1-generating circuit 51 and a W2-generating circuit 52 are provided, respectively. The block address W1, control and ID code W2 each consist of one word of 8 bits, and the parity generation circuit 53 generates a parity code P for W1 and W2.

The control and ID code W2 is formed based on information from the system controller. PCM audio signal from input terminal 9, block address W1
, control and ID code W2, and parity code P are sequentially selected by the selector 54, and the data to be recorded in the audio area 86S is output from the selector 54.

The output data of the selector 54 is supplied to a modulation circuit 55 for 8-10 modulation. 8-10 modulation is a type of digital modulation that converts 8 data bits per word into 10 channel bits to reduce the DC component of recorded data.

The output data of the modulation circuit 55 is supplied to a synchronization signal addition circuit 56, and a synchronization signal S is applied to each block of data.
YNC is added. The output data of the synchronization signal addition circuit 56 is supplied to the parallel/serial conversion circuit 57, and the output terminal 10
Serial data is extracted.

FIG. 5 shows the audio reproduction processing circuit 8a (8
The same applies to b). Reproduction data from the input terminal 15 is passed through a reproduction equalizer 61 to the serial/parallel conversion circuit 6.
2 and PLL63. A clock synchronized with the reproduced data is formed by the PLL 63. This clock is used to process the reproduced data. The output data of the serial/parallel conversion circuit 62 is supplied to a synchronization detection circuit 64 to detect a block synchronization signal. A timing signal formed based on the detection of this block synchronization signal is also used to process the reproduced data. The synchronization detection circuit 64 performs synchronization detection only when a window pulse WP output from a window pulse generation circuit 71, which will be described later, is supplied.

The output data of the synchronization detection circuit 64 is 8-10.
The signal is supplied to a modulation demodulation circuit 65, and the 10-bit data is converted into 8-bit data. The output data of the demodulation circuit 65 is supplied to the selector 66, and the selector 66 outputs P
A CM audio signal, block address W1, control and ID code W2, and parity code P are separated.

A PCM audio signal is output from output terminal 16, and block address W1, control and ID code W2 are stored in registers 67 and 68, respectively. Block address W1, control and ID code W2 from registers 67 and 68, and parity P from selector 66 are supplied to parity check circuit 69, and errors regarding block address W1, control and ID code W2 are detected. Block address W1 from register 67
is supplied to the address generation circuit 70, and an address for writing the PCM signal into the memory 6 is formed at the output terminal 17. Furthermore, the control and I
D code W2 is provided to the system controller and used for control and display purposes.

The block address W1 is further supplied to the window pulse generation circuit 71, and the block address W1 is
1, a window pulse WP as shown in FIG. 7 is generated, and the synchronization detection of the synchronization detection circuit 64 is controlled by this window pulse WP. That is, control is performed so that only data enclosed between the preamble and postamble is synchronously detected. Therefore, even if there is data remaining after the postamble as shown in FIG. 11(d), it will not be synchronously detected and written to the subsequent memory 6.

The window pulse generating circuit 71 is supplied with pulses (PG pulses) output in synchronization with the rotation of the rotary drum 84. The rising timing of the window pulse WP is regulated by the PG pulse.

FIG. 6 shows a specific example of the window pulse generation circuit 71, in which the PG pulse (FIG. 7) is supplied to the set terminal of the flip-flop 78, and the block address W
The comparison output related to 1 is supplied to the reset terminal, and the pulse output from this flip-flop 78 is used as the window pulse WP (FIG. 7).

Therefore, the output of the W1 register 67 is supplied to the block address detection circuit 73, and the block address W1 is detected. The block address W1 is supplied to the calculation circuit 75, and the remaining block number DB is calculated based on this block address W1.

The remaining block number DB is supplied to the load terminal of the counter 74, and the detection pulse generated from the block address W1 is supplied to the preset terminal PR. The reproduction word pulse supplied to the terminal 76 (therefore, one block has 35 word pulses) is used as the clock. Therefore, the counter 74 is loaded with the calculation output DB each time in synchronization with the timing at which the block address W1 is obtained, and its value is counted down using the reproduced word clock. 4 postamble detection blocks
As the ninth block, the detected block address W
If block number 1 is conveniently designated as WN, then (49-W
N)×42=DB becomes the calculation output. Here, the constant "4
2" is a number that takes into account the jitter of the reproduced word pulse when the PLL 63 is out of synchronization due to dropouts, etc. One block consists of 35 words, and the jitter of the reproduced word pulse is +/-20 per block. %, and the number (35×1.2=42) is set so that the postamble can be detected correctly even when there is this jitter.

[0063] The count output is the loaded calculation output DB
is "0", that is, when the 49th block address W1 is detected, or when the calculation output loaded by the last detected block address W1 counts down and becomes "0", "0"
become.

The counter output is supplied to comparator 77. When the counter output is "0", the flip-flop 78
is reset, so the window pulse WP falls. As shown in FIG. 7, the window pulse WP when the 49th block address W1 is detected is shown by a solid line. The broken line indicates when the counter output reaches "0" after counting down. In the case of the broken line, there is a possibility that there is a deviation of plus or minus 20% due to the jitter of the reproduced word clock, but in either case, it will fall within the postamble.

The counter 74 detects that the output of the comparator 77 is "-
1, the counter operation stops.

If the window pulse generating circuit 71 is configured to load the output DB of the arithmetic circuit 75 each time according to the detected block address W1 as described above, when the 49th block, that is, the postamble is detected, The calculation output DB "0" is loaded, and the window pulse WP immediately falls, so that the postamble can be detected correctly. Also, due to dropout etc., the block address W of the 49th block
Even when 1 is not detected, since the calculation output DB based on the last detected block address W1 is supplied to the counter 74, the position of the postamble can be correctly detected using this calculation output DB.

The number of blocks in the postamble described above is 1.
The number of blocks above is sufficient and is not limited to the embodiment, and the reason why the number of blocks is set to 2 as in the embodiment is that even if the 49th block cannot be detected, the postamble can be reliably detected at the 50th block. It is.

[0068] A tape or a disk can be used as the recording medium for digital data, and as the writing and reading means, in addition to magnetic means, optical means, opto-magnetic means, etc. can be used.

[0069]

As described above, the present invention includes digital data, a preamble including a plurality of sync block data added to the preceding stage, and a preamble including sync block data added to the latter stage of the digital data, and the preamble. A postamble composed of fewer blocks than the number of constituent blocks is recorded at the same time.

[0070] According to this, the number of constituent blocks of the postamble can be reduced, so that high-density recording is possible. In addition, since the position of the postamble can be detected correctly even if the number of blocks constituting the postamble is reduced, there is no possibility of accidentally reusing the data remaining after erasing.

Therefore, the present invention is suitable for application to high-vision VTRs, 8 mm VTRs, etc. that record audio signals in addition to video signals using PCM.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a data format according to the present invention.

FIG. 2 is an explanatory diagram of operations during after-recording.

FIG. 3 is a system diagram showing an example of a recording/reproducing apparatus according to the present invention.

FIG. 4 is a system diagram showing an example of an audio recording processing circuit.

FIG. 5 is a system diagram showing an example of an audio reproduction processing circuit.

FIG. 6 is a system diagram showing an example of a window pulse generation circuit.

FIG. 7 is an explanatory diagram of window pulse operation.

FIG. 8 is a plan view of the rotating drum system.

FIG. 9 is a diagram of a tape pattern used to explain the present invention.

FIG. 10 is a diagram of a signal format as well.

FIG. 11 is an explanatory diagram of an after-recording operation.

FIG. 12 is a diagram showing another example of a signal format.

[Explanation of symbols]

1 Video signal processing circuit 6 Memory 7a, 7b Audio recording processing circuit 8a, 8b
Audio playback processing circuit 64 Synchronization detection circuit 67 W1-register 71 Window pulse generation circuit 73 Block address detection circuit 74 Counter 75 Arithmetic circuit 77 Comparator 78 Flip-flop Ha~Hd Head

Claims (3)

[Claims] Claim 1: A preamble including digital data, a plurality of sync block data added before the digital data, and sync block data added after the digital data, and with a number of blocks smaller than the number of blocks. A digital data recording and reproducing device characterized in that configured postambles are simultaneously recorded. 2. When reproducing digital data to which a postamble including a plurality of sync block data is added, a detection means is provided for detecting sync block data inserted in the postamble, and based on the detection output, 1. A digital data recording and reproducing apparatus characterized in that valid data of reproduced digital data is determined by 3. Recording digital data to which a preamble and a postamble are added on a part of a diagonal track,
A digital data recording and reproducing apparatus characterized in that the reproduced digital data is obtained by reproducing the postamble data, and the reproduced digital data immediately before the postamble data is detected is used as valid data.