SU1666964A1 - Rotation frequency meter - Google Patents

Abstract

The invention can be used in devices for measuring rotational speed. The purpose of the invention is to increase reliability and accuracy. The goal is achieved in that JK-trigger 4, shaper 7 clocks, counters of odd 8 and even 9 pulses, odd and even decoders 10, 11, shift register 12, second RS-trigger 6, second element Both control 14 and prohibit block 2, which contains a JK correction trigger, a control JK trigger, pulse drivers, five AND elements, a prohibition element, first and second OR elements, and a delay element. The device also contains a pulse speed sensor 1, a pulse counter 3, control element 13 and an RS flip-flop 5. The essence of the invention is to exclude the loss of sensor pulses due to the asynchronism of the sensor and interrogation signals. This is achieved by organizing the storage of the input pulse when it is not synchronized with the interrogation signals until the end of the inhibit signal. 1 hp f-ly, 7 ill.

Description

The invention relates to measurement and information technology and can be used in devices for measuring rotational speed.

The aim of the invention is to increase reliability and accuracy.

FIG. 1 is a functional diagram of a device for measuring rotational speed; in fig. 2 - the block diagram of the ban 2 is functional; in fig. 3 — timing diagrams for the operation of the device; in fig. 4–7 are timing diagrams explaining the operation of the prohibition unit 2.

A device for measuring the rotational speed contains (Fig. 1) a pulse frequency sensor 1, a prohibition unit 2, a pulse counter 3, a JK trigger 4, the first 5 and the second 6 RS triggers. shaper 7 clocks, counters of odd 8 and even 9 pulses and their corresponding odd 10 and even 11 decoders, shift register 12, first 13 and second 14 AND control elements.

In the device for measuring the rotational speed, the pulse frequency sensor 1, the inhibit unit 2 and the pulse counter 3 are connected in series, the outputs of the pulse counter 3 are connected to the data inputs of the shift register 12, the output of which is connected to the first input of the second control element 14, the output of which the output of the device, and the second input of the second element And 14 control is connected to the shift input of the shift register 12 and the output of the first control element And 13, the first input of which is connected to the output of the JK-flip-flop 4, the inputs of which are J- and K- are connected, respectively, to the bus levels of logic 1 and logic O, and the reset input is connected to the initial installation bus 15, with the first reset inputs of the first and second RS-flip-flops 5, 6, respectively, with the installation input of the prohibition unit 2, with the reset inputs counters 8, 9, odd and even pulses, the polling bus is connected to the second input of the first control element I 13 and to the input of the clock generator 7, the first output of the last of which is connected to the information input of the odd pulse counter 8 and the control input of even the encoder 11, the information inputs of which are connected to the outputs of the counter 9 even pulses, the information input of which is connected to the second output of the clock generator 7 and to the control input of the odd decoder 10, the information outputs of which are connected to the outputs of the counter 8 of odd pulses, the first output of the odd decoder 10 is connected to the input of the record of the shift register 12, the recording resolution of which is connected to the output of the second RS flip-flop

6, the installation input of which is connected to the first output of the even decoder 11 and to the installation input of the first RS flip-flop 5, the output of the last of which is connected to the inhibit input of the prohibition block 2, the second output

0 odd decoder 10 is connected to the second reset input of the first RS flip-flop 5 and to the sync input of JK flip-flop 4, the second output of the even decoder 11 is connected to the second reset input of the second

5 RS flip-flop bis the first reset input of the counter 3 impuls, the second reset input of which is connected to the general reset bus (OS),

The prohibition block 2 contains (FIG. 2) JK0 correction trigger 16, JK-control trigger 17, first 18, second 19, third 20 and fourth 21 pulse shapers, elements 21-1, 21-2, 21-3, 21- 4, 21-5, prohibition element 22, elements OR 23-1,

5 23-2 and element 24 delay.

In block 2 of the ban, the input of the block of the ban is connected to the input of the first driver 18 pulses, the output of which is connected to the first inputs of the first and second elements And 21-1, 21-2, to the input of the delay element 24, the output of which is connected to the first inputs of the fourth and And 21-4, 21-5 elements, the second inputs of which are interconnected and connected to

5 synchronization input JK-trigger 17 controls and to the output of the element 22 of the ban, the first input of which is connected to the output of the JK-trigger 16 correction, J and K-inputs of which are connected, respectively, to the wide logical levels O and 1, the installation setting JK -trigger 16 correction is connected to the output of the second element And 21-2, the second input of which is connected to the first input of the third element And 21-3, the output

5 of which is connected to the synchronization input of the JK-correction trigger 16, the reset input of which is connected to the reset input of the control JK-trigger 17 and is the installation input of the prohibition unit 2, the second input

0 of the third element And 21-3 connected to the output of the third pulse shaper 20, the input of which is connected to the output of the first element a And 21 -1, the second input of the last of which is connected to the first input of the first

5 of the element OR 23-1, the input of the second pulse shaper 19 and is the inhibit input of the prohibition unit 2, the output of the second pulse shaper 19 of the pulses is connected to the inhibit input of the inhibit element 22 and to the first input of the third And 21-3 element the input of the first element OR 23-1, the output of which is connected to the second input of the prohibition element 22, the J and K inputs of the JK control trigger 17 are connected to the logic levels O and 1, respectively; the output of the fourth element 21-4 is connected to the installation input of the JK-trigger 17 control, out one of which is connected to the input of the fourth pulse former 21, the output of the fifth element 21 21 is connected to the first input of the second element OR 23-2, the output of the fourth pulse former 21 is connected to the second input of the second element OR 23-2, the output of which is output block 2 ban.

FIG. 3 shows time diagrams explaining the operation of the device, where a) is the sign of the beginning of the survey; b) polling pulses at the input of the forcing device 7; c) the first output of the even decoder 11; d) the first output of the odd decoder 10; d) the second output of the even decoder 11; e) the second output of the odd decoder 10; g) resolution of recording of the pulse counter 3; h) output JK-trigger 4; i) reading; k) prohibition.

FIG. 4-7 shows the time diagrams for the operation of the prohibition unit 2, where a) the prohibition input of the prohibition unit 2; b) the output of the imaging unit 18 pulses; C) the output of the imaging device 19 pulses; g) the output of the imaging unit 20 pulses; d) the output of the element 22 of the ban, e) the output of the block 2 of the ban.

The device works as follows.

Frequency sensor 1 generates pulses with a frequency proportional to the frequency of rotation of the input shaft, arriving in the absence of a signal at the prohibition input of the prohibition unit 2 on the counting input of the counter 3 pulses. From the information processing unit or the digital computer, the bus 15 receives impulses of the sign of the beginning of the survey (PNO) and the polling pulses of the bus Interrogation. The PNO pulse sets the initial state of all the memory elements, except for the 3-pulse counter.

Further, the polling pulses on the shaper 7 clock pulses are converted into two series of pulses — an odd 1T and an even 2T, which are considered respectively to be counters of odd 8 and even 9 pulses. The counting results are decrypted by decoders: odd 10 and even 11, with counter 8 counting 1T decrypted with a decoder gated with a 2T pulse, and counter 9 counting 2T with a decoder gated with a 1T pulse. The first polling pulse 1A sets the first 5 and the second 6 RS triggers that produce

accordingly, the prohibition signals on the prohibition block 2 and the information recording enable signal in the shift register 12 (FIG. 3K. g). The second impulse 2I rewrites information from the counter of 3 impulses to the shift register 12. Then, the third PID pulse polls off the write enable signal to the shift register 12 and resets the 3 pulse counter to the initial state. Following

0 pulse 4and, setting the first RS flip-flop 5 to the state O, removes the inhibit signal and, setting 1 J to the flip-flop 4, allows the polling pulses to pass through the first control element 13 to the shift input of the shift register 12. These pulses shift the information in the register 12 with the falling edge, front gate of the second control element 14, the output of which will generate the pulses of the sequential code, the value of which corresponds to the number of pulses counted by the counter of 3 pulses.

The principle of operation of the prohibition unit 2 is that the second 19 and third 20 pulse shapers form a duration longer than the duration of the input pulse generated by the first driver 18. The input pulse from the output of frequency sensor 1 coincides with the leading edge of the prohibition signal (Fig. 4) It passes through the block 2 on the counter 3. The same happens in the case of a pulse shifting the input frequency by the pulse width of the input relative to the bar signal (Fig. 5). The input pulse is memorized until the end of the inhibit signal, if the input frequency pulse is in the middle of the inhibit signal during polling (Fig. 6). Memorization

0 also occurs when the input frequency pulse coincides with the falling edge of the inhibit signal (Fig. 7).

The leading edge of the signal at the input JK-triggers 16, 17 are set to 1, and

5 is then set to state O by a falling edge, for example, from a high level to a low. The pulse former 19 generates a signal from the rise of the prohibition signal from a low level to

0 high, and the driver 20 - with the coincidence of the signals at the input and prohibition using the first element And 21-1.

At the same time, the signal from the output of the pulse former 19 prohibits the passage of information through the prohibition element 22. The magnitude of the delay of the delay element 24 is chosen in such a way as to overlap the operation of all elements of the blocking path of block 2. Pulse shaper 18 is necessary to form

the standard duration of the input pulse, and the driver 21 for generating a signal at the output of the prohibition block 2 in case the input signal (the signal from the output of the frequency sensor 1) is memorized on the JK control trigger 17.

Thus, the pulses generated by the frequency sensor are not lost when any interrogation signals and the sensor are in sync.

Claims (2)

Claim 1. A device for measuring rotational speed, comprising a pulse frequency sensor, a pulse counter, an AND control element and an RS flip-flop, characterized in that, in order to increase reliability and accuracy, a prohibition block, a JK flip-flop, driver of clock pulses, odd and even pulse counters, odd and even decoders, shift register, second RS flip-flop and second control element, with pulse frequency sensor, prohibition unit and pulse counter connected in series, pulse counter outputs The pulses are connected to the data inputs of the shift register, the output of which is connected to the first input of the second control And, the output of the last of which is the output of the device, and the second input of the second element And is connected to the shift input of the shift register and the output of the first control And, the first input connected to the output of the JK-flip-flop, whose inputs J- and K- are connected, respectively, to the buses of logic level 1 and logical O, and the reset input is connected to the initial setup bus, with the first reset inputs of the first and second RS-trigger respectively, with the input of the prohibition unit, with the reset inputs of the even and odd pulse counters, the interrogation bus is connected to the second input of the first control element AND and the input of the clock generator, the first output of which is connected to the information input of the odd pulse counter and the control input an even decoder, the information inputs of which are connected to the outputs of the counter of even pulses, the information input of which is connected to the second output of the clock interval generator and to the input control of the odd decoder, whose information outputs are connected to the outputs of the odd pulse counter, the first output of the odd decoder is connected to the write input of the shift register, the write resolution of which is connected to the output of the second RS flip-flop, the installation input of which is connected to the first output of the even decoder and to the input installation of the first RS-flip-flop, the output of the last of which is connected to the prohibition input of the prohibition block, the second output of the odd decoder is connected to the second reset input of the first RS-flip-flop and Valid synchronization JK-flip-flop, the second output of the decoder even coupled to a second reset input of the second RS-trigger and to a first input 0 pulse counter reset, the second reset input of which is connected to the general reset bus. 2. The device according to claim 1, characterized in that the prohibition unit contains JK-trigger 5 correction hero, JK-control trigger, first, second, third, fourth pulse formers, five AND elements, a prohibition element, the first and second elements OR and the delay element, and 0 the input of the prohibition unit is connected to the input of the first pulse generator, the output of which is connected to the first inputs of the first and second elements I, to the input of the delay element whose output is connected to the first inputs of the fourth and fifth elements I, the second inputs of which are interconnected and connected to the sync input of the JK control trigger and to the output of the inhibit element, the first input of which is connected to the output of the correction JK trigger, the J and K inputs of which are connected respectively to the logic level buses O and 1, the installation input The correction JK trigger is connected to the output of the second element I, the second input of which is connected to the first input of the third element I, the output of which is connected to the synchronization input of the JK correction trigger, whose reset input is connected to the reset input JK-trigger of the control and is input installation of the prohibition unit, the second input of the third element And is connected to the output of the third pulse generator, the input of which is connected to the output of the first element And, 5 the second input of the last of which is connected to the first input of the first element OR, the input of the second pulse shaper and is the input of the prohibition of the prohibition block, the output of the second driver of the pulse is connected to the input of the prohibition of the element and to the first input of the third element I, the second input of which is connected to the second the input of the first element OR whose output is connected to the second input of the element 5 prohibitions, the J and K inputs of the JK control trigger are connected respectively to the logic level buses O and 1, the output of the fourth element I is connected to the installation input of the JK control trigger, the output of which is connected to the input of the fourth pulse shaper, the output of the fifth element I connected to the first input of the second element OR, the output of the fourth driver the pulses are connected to the second input of the second OR element, the output of which is with the output of the inhibiting unit. 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